JP2009170650A - Semiconductor integrated circuit and its placement and routing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an effective placement of cells which suppresses power supply noise to a level having no impact on a neighboring circuit without disturbing the regularity of placement of circuit cells. <P>SOLUTION: A semiconductor integrated circuit includes a trunk interconnect (e.g. 2S) wired in one direction, a plurality of branch lines (e.g. 20S) branched from a plurality of trunk interconnect points arranged at an equal interval, a plurality of cell lines each including a local voltage line (e.g. a virtual VSS line 30S) provided for each branch line, a switch between the local voltage line and the branch line, and at least one circuit cell connected with the local voltage line, and a plurality of control lines CL1-CL4 for connecting a predetermined number of switches (e.g. pairs of SW1, SW2, and the like) included in a plurality of cell lines separated from each other while holding one or more cell lines therebetween such that the predetermined number of switches is controlled simultaneously. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a power supply voltage or a reference voltage is applied to a circuit cell by a trunk wiring and a plurality of branch lines branched from the trunk wiring, and a layout wiring method thereof. In particular, the present invention relates to a semiconductor integrated circuit having a connection structure of a control line with respect to a switch that is controlled to be turned on and off to shut off the power supply, and a method for arranging and wiring the semiconductor integrated circuit, including a method for determining a switch to be connected to the control line And about.

An MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor) technique is known as a circuit that controls the interruption and release of power supply by a switch.
MTCMOS technology aims to prevent signal delay, lowers the threshold voltage of the transistor to a value suitable for power supply voltage reduction and device miniaturization, while leaking to a stopped circuit by a transistor with a larger threshold voltage. The current path is interrupted to prevent waste of power consumption.

In the application of the MTCMOS technology to a circuit block, a wiring (local voltage line) locally provided in the circuit block, which is referred to as a so-called virtual VDD line or virtual GND line, is provided. The local voltage line is a switch for shutting off and releasing the power to the actual power line (actual VDD line) and the actual reference voltage line (actual VSS line) arranged as a global voltage line common outside the circuit block. Connected through.
There are three places where the switch is provided, between the functional circuit that is repeatedly activated and deactivated and the actual VDD line, and between the functional circuit and the actual VSS line. An NMOS transistor is used on the transistor, actual VSS line side.

  The activation and deactivation of the functional circuit of the MTCMOS application block is performed by a circuit in the MTCMOS non-application block that is always in operation after receiving power supply from the actual VDD line and the actual VSS line after the semiconductor integrated circuit is activated. Be controlled. The MTCMOS non-applicable block mainly includes a clock generation circuit, other repeater buffers, and other circuits for controlling the entire IC, inputting / outputting signals and holding data, and turning on / off the switch for controlling the power-off. A switch control circuit is included for controlling.

In the MTCMOS application block, if the stop time is long, the local voltage line, for example, the virtual VSS line, may be charged by the leakage current of the internal circuit and rise to a high potential close to the real VDD line. Therefore, when the power cutoff switch is turned on when the MTCMOS application circuit block is restarted, a sudden current flows into the actual VSS line due to the discharge of the virtual VSS line. This current is called an inrush current (Rush Current) or the like. When the inrush current flows into the actual VSS line, it becomes a positive noise voltage, changes the VSS potential of the circuit in the MTCMOS application block, and is further transmitted to the neighboring MTCMOS non-application block.
A similar phenomenon may occur in the actual VDD line. However, since a sudden current flows out from the actual VDD line, it differs from the above case in that a negative noise voltage is generated in which the potential of the actual VDD line rapidly decreases.

  In any case, these noise voltages (power supply noise) are transmitted to a clock generation circuit or a repeater buffer that is operating in a nearby circuit, and as a result, the power supply voltage amplitude decreases rapidly, resulting in an operation delay. Will affect.

As a countermeasure against power supply noise, for example, in Non-Patent Document 1, a plurality of PMOS switches are connected in parallel between a global real VDD line and a local virtual VDD line, and a control signal is forwarded to these gates while being delayed. Thus, a technique for gradually reducing the connection impedance is disclosed. In this technique, a plurality of buffer circuits (inverter series circuits) for delaying a control signal are provided, and one control signal is sequentially delayed by the plurality of buffer circuits.
Philippe Royannez etc, “90nm Low Leakage SoC Design Techniques for Wireless Application”, 2005 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, P138.

However, the technique described in Non-Patent Document 1 has a drawback that it takes time to control although the peak of power supply noise can be suppressed.
In addition, a plurality of switches and a large number of inverters for delaying the control signal are required, and the arrangement area is relatively large. This arrangement area is discretely arranged in each of the row (row) direction and the column (column) direction when looking at the chip photograph in Non-Patent Document 1, but because the area of each arrangement area is large, Such an arrangement of switches or the like disturbs the regularity of the arrangement of circuit cells, and an efficient cell arrangement cannot be performed.

  Further, when manufacturing variations occur in transistors or the like, it may occur simultaneously that a current larger than the value estimated at the time of design by the transistor of the switch and a delay time due to the inverter are shortened. On the contrary, the switch current value may be reduced and the delay time may be increased. For this reason, the technique described in Non-Patent Document 1 has a problem that it is very difficult to design the power supply noise to a certain level or less.

  A semiconductor integrated circuit according to one aspect of the present invention includes a trunk wiring that is wired in one direction and to which a power supply voltage or a reference voltage is applied, and a plurality of branches that are branched from a plurality of trunk wiring portions that are equally spaced in the one direction. Each branch line, a local voltage line provided for each branch line, and at least one circuit cell connected to the local voltage line, each connected between the local voltage line and the branch line A plurality of cell lines in which arrangement (number and position) and non-arrangement of at least one switch are determined in advance, and a plurality of cell lines separated from each other across one or more cell lines in the plurality of cell lines And a plurality of control lines for connecting a predetermined number of the switches so as to be simultaneously controllable.

In one aspect of the present invention, the first and second switches of two cell lines controlled simultaneously by one control line are preferably arranged at a pitch of the number n of cell lines (n: an integer of 2 or more), respectively. When the first switch is placed at an equal distance from the trunk wiring and the first switch is turned on to activate the circuit cell, the first cell line including the first switch changes from the first cell line to the cell line including the second switch. In a plurality of circuit cells included up to the nth cell line cell line adjacent on the cell line side, in a current path from the first switch to a main wiring portion provided with a branch line connected to the second switch A potential drop (IR drop) is generated for each cell line when the plurality of circuit cells are operated, and a total of n operating IR drops generated in the current path starting from each circuit cell. As a value below the cell line number n is determined.
More preferably, between two cell lines including the first and second switches arranged at a pitch of the number n of cell lines, a switch of another cell line is a pair (however, if a fraction is generated, it is a pair. The first and second switches are first turned on when the circuit cell is activated, and the interval between the two cell lines including the paired switches becomes smaller from the larger one. A switch control unit configured to control the other control line for switching on;

According to the above configuration, the wiring for supplying the power supply voltage or the reference voltage is configured to include a unidirectional trunk wiring and a plurality of branch lines branching from the equally spaced locations in the middle. A cell line is provided for each branch line. All or some of the cell lines include one or more switches. The switch is a so-called power cutoff switch that controls connection and disconnection between the local voltage line and the branch line for each cell line. Therefore, in the present invention, the switch is arranged as a cell in the cell arrangement region. Desirably, each of the switches is arranged equidistant from the main wiring. That is, the same number of switches as the cell lines are arranged in parallel with the main wiring.
Control lines are connected to the plurality of switches arranged in this manner so that a predetermined number of switches included in a plurality of cell lines separated from each other with one or more cell lines interposed therebetween can be simultaneously controlled.

  When the switch is embedded in the cell arrangement area as described above, the cell arrangement rules (cell width, height (width and length perpendicular to the line), etc.) are followed. In the present invention, the switch is turned on. The charge discharge capability is controlled by the number of switches that are simultaneously controlled. For this reason, even if the charge discharging capability of each switch is relatively small, for example, when a charge discharging capability equivalent to a switch with a large gate width is required, the number of simultaneously controlled switches can be arbitrarily increased, It is possible to freely design the switch capacity without disturbing the cell arrangement rule.

Further, separating two switches controlled at the same time by one or more cell lines has an effect of reducing the peak of power supply noise as described below.
For example, taking a case where a reference voltage is applied to a trunk line or a branch line as an example, the local voltage line may be charged to a level close to the power supply voltage due to the leakage current described above. When the switch is turned on at this time, an inrush current (in terms of voltage, power supply noise) reaches one end (voltage supply side end) of the trunk wiring through the branch line. The longer this current path is, the more the IR drop expressed by the product of the current amount (I) and the path equivalent wiring resistance (R) is larger, so that the power source noise is attenuated, which is desirable.

When a switch pair to be controlled simultaneously is selected in two adjacent cell lines, it is desirable to dispose this pair far from the voltage supply side end of the trunk line because the attenuation amount of power supply noise generated when the switch pair is conductive is large. However, after that, the room for selecting another switch pair with a low attenuation is narrowed.
In other words, when repeatedly selecting the switch pairs to be turned on sequentially, it is desirable to select the switch pairs far from and close to the voltage supply side end. “Separating two switches into one or more cell lines” is the basis of switch selection in order to average the IR drop amount and prevent the occurrence of peak power supply noise protruding as a whole block.

  In particular, the switch pair selected first switches between the wirings held at the maximum initial voltage difference (for example, a voltage difference close to the power supply voltage) during control. It affects the delay of circuit blocks.

For this reason, in a preferred embodiment of the present invention, conditions for the switch arrangement that are simultaneously selected in pairs are defined.
In the case of selecting a switch pair, if the arrangement pitch of the two switches is defined by the number of cell lines n, the size of the n is expressed as “other switch (first switch) when one switch pair (first switch) is turned on. The IR drop of the current path to the main wiring portion provided with the branch line connected to (2 switches) is equal to or less than the total value of the n operation IR drops generated in the current path existing for each cell line during the normal operation. N is determined as the value ”.
In addition, when there are three or more switches that are simultaneously selected, it is only necessary that the above condition is satisfied by any two adjacent switches.

  The meaning is that “the total value of IR drop during normal operation is designed so that neighboring circuit cells operate normally without delay even if there is potential fluctuation of the reference voltage line due to this. As long as the peak value of the power supply noise generated by turning on the switch pair does not exceed the total value, there is no delay effect on neighboring circuit cells. The above definition regarding the size of n indicates this in relation to the size of the IR drop.

  According to one embodiment of the present invention, there is provided a method for arranging and wiring a semiconductor integrated circuit, wherein a power supply voltage or a reference voltage applied to a trunk wiring wired in one direction is branched from a plurality of trunk wiring locations equally spaced in the one direction. Connection to a control line of a switch for controlling connection between a local voltage line connected to a circuit cell and a branch line within a predetermined cell line with respect to a plurality of cell lines distributed through the plurality of branch lines formed A method for arranging and wiring a semiconductor integrated circuit, comprising: determining an arrangement pitch n (n: an integer of 2 or more) of two cell lines including two first and second switches controlled simultaneously by the control line A step of arranging and wiring the plurality of cell lines and the plurality of branch lines; a step of arranging the trunk wiring in a direction orthogonal to the cell lines and connecting to the plurality of branch lines; A step of arranging and wiring at least one of the control lines, wherein the plurality of switches are connected to one of the control lines for simultaneous control in a plurality of cell lines separated from each other by the arrangement pitch n or more. And determining the wiring pitch n from the first cell line including the first switch to the cell line including the second switch when the first switch is turned on to activate the circuit cell. In a plurality of circuit cells included up to the n-th cell line adjacent on the one cell line side, it occurs in a current path from the first switch to a main wiring portion provided with a branch line connected to the second switch. A potential drop (IR drop) exists for each cell line when the plurality of circuit cells are operated, and occurs in the current path starting from each circuit cell. Operation to be equal to or less than the sum of the IR drop, determining the wiring pitch n.

According to the present invention, since the switch for controlling the power shutdown and the release thereof is embedded in the cell arrangement region, the switch arrangement does not disturb the arrangement regularity of the circuit cell, and the arrangement efficiency is high and useless. Space is unlikely to occur.
In addition, a predetermined number of switches separated from each other can be selected by the control line so as to be simultaneously controllable, and at this time, the peak of power supply noise can be suppressed to the extent that it does not affect the operation of neighboring circuit cells.

  Embodiments of the present invention will be described below with reference to the drawings.

<Basic structure>
FIG. 1 is a diagram illustrating an example of a layout of a semiconductor integrated circuit according to the present embodiment.
In FIG. 1, a plurality of input / output cells 40 are arranged in rows along four sides of a rectangular semiconductor chip on which a semiconductor integrated circuit is formed. In the chip area surrounded by these input / output cells 40, the actual VDD line 2D and the actual VSS line 2S are arranged in pairs. More specifically, the actual power supply line pairs (2D, 2S) are arranged in parallel in the row (row) direction and the column (direction) of the circuit block arrangement region, thereby forming a grid-like power supply line arrangement. Further, the actual power supply line pair (2D, 2S) surrounds the periphery of the lattice portion by the outer frame portion, and gives many feeding points to the lattice portion from the outer frame portion.
These real power supply line pairs (2D, 2S) are each formed in the row direction and the column direction from metal layers of different layers in the multilayer wiring structure. Therefore, the real VDD line 2D and the real VSS line 2S are , Can be electrically isolated and crossed.

The chip area is divided by the grid portion and the outer frame portion of the actual power line pair. A circuit block (hereinafter referred to as a non-application circuit block) 30 to which the MTCMOS technology is not applied is arranged in the relatively divided area. In addition, circuit blocks to which a large number of MTCMOS technologies are applied (hereinafter referred to as MTCMOS circuit blocks) are arranged in large and small divided areas. Here, blocks other than the non-applicable circuit block 30 are MTCMOS circuit blocks, and one of them is indicated by a reference numeral “1” in the figure.
In the figure, the MTCMOS circuit block 1 and the like are all connected to the actual power supply line pair (2D, 2S). On the other hand, the actual power supply line pair (2D, 2S) seems to be unconnected to the non-applicable circuit block 30, but the actual power supply line pair (2D, 2S) is actually connected to the non-applicable circuit block 30. Has been.

FIG. 2 schematically shows one real VSS line 2S or real VDD line 2D of the MTCMOS circuit block 1 and a partial configuration around it. Hereinafter, the case of the actual VSS line 2S will be described.
As shown in FIG. 2, the actual VSS line 2S is a kind of global voltage line that is used in common with other circuit blocks and widely disposed in the semiconductor chip, and is formed by a relatively upper metal layer. The actual VSS line 2S extends in one direction (here, the column direction) and crosses the MTCMOS circuit block 1.
Branch lines 20S extend from a plurality of equally spaced locations (shown by black circles) of the actual VSS line 2S in the other direction (here, the row direction orthogonal to the column direction). Since the branch line 20S is branched from the connection point indicated by the black circle of the actual VSS line 2S, the actual VSS line 2S corresponds to “stem wiring”. The plurality of branch lines 20S are arranged in parallel to each other. When the trunk wiring is the actual VDD line 2D, the branch line is indicated by the reference numeral “20D” instead of the reference numeral “20S”.
In this example, a reference voltage VDD (for example, a GND voltage) applied outside the circuit block is supplied to the actual VSS line 2S, and this voltage is transmitted to the branch line 20S.

On the other hand, a virtual VSS line 30S as a local voltage line is arranged in each separated space of the branch line 20S in parallel with the neighboring branch line 20S. The virtual VSS line 30S is referred to as a virtual VDD line 30D when the trunk wiring is the real VDD line 2D.
The virtual VSS line 30S is formed of a metal layer, a polysilicon layer, or the like below the actual VSS line 2S, which is a trunk line, together with the branch line 20S.
Here, a plurality of virtual VSS lines 30S are connected to each other by a column-direction virtual VSS connection line 3S made of an upper metal layer or the like. Note that the virtual VSS connection line 3S is referred to as a virtual VDD connection line 3D when the trunk wiring is the real VDD line 2D.
Unlike the actual VSS line 2S and the like, the virtual VSS line 30S and the virtual VSS connection line 3S are not always supplied with a predetermined voltage. Depending on the operating state of the circuit, the voltage of the virtual VSS line 30S changes dynamically, such as being lowered to the reference voltage VSS and being fixed, being in an electrically floating state, or being gradually charged by a leakage current. .

In FIG. 2, switches SW1 and SW2 are provided between the branch line 20S and the virtual VSS line 30S at two locations. The switches SW1 and SW2 are MTCMOS switches that control the power-off and release of the MTCMOS.
The cell placement and routing is performed so that circuit cells are arranged in a line in the longitudinal direction in a chip region that is long in the row direction defined by one branch line 20S and the adjacent virtual VSS line 30S. This chip region long in the row direction corresponds to a “cell line”.
Although only two switches are shown in FIG. 2, at least one switch SW1, SW2 is provided for each cell line. Alternatively, a cell line including a switch and a cell line not including a switch are arranged according to a predetermined rule.
In any case, FIG. 2 shows only two switches SW1 and SW2 that are simultaneously controlled, and these switches SW1 and SW2 are arranged as one cell or provided as a part of a circuit cell.

FIG. 3A and FIG. 3B show examples of arrangement of switches in a cell.
In the example of FIG. 3A, the circuit cell 4A is configured by only the switch SW as an active element, and in the example of FIG. 3B, the switch SW is included in the same circuit cell 4B together with the logic circuit portion 5.
In FIG. 3, an NMOS transistor is shown as the switch SW for controlling the cutoff of the reference voltage VSS. In this case, the in-cell elements of the branch line 20S to which the reference voltage VSS is applied, the branch line 20D to which the power supply voltage VDD is applied, and the virtual VSS line 30S are included in the circuit cell as illustrated.
As shown in FIGS. 3A and 3B, the switch SW is connected between the branch line 20S and the virtual VSS line 30S, and the logic circuit unit 5 is connected between the branch line 20D and the virtual VSS line 30S. .
It is not always necessary to form these wirings simply by connecting the elements in the cell by cell arrangement, and the cells may be connected by upper layer wiring. In short, in the present embodiment, it is sufficient that one cell line includes one local voltage line, one switch SW, and one or more circuit cells.

The switches SW are commonly connected in a required combination by an upper control line CL. For example, the switches SW1 and SW2 in FIG. 2 are commonly connected by one control line. For this purpose, it is desirable that the switches SW1 and SW2 are arranged at the same distance from the actual VSS line 2S.
This distance may vary, but in that case, the control line needs to have a branch structure, which is not desirable.

<Basic concept of placement and routing>
During normal operation, that is, the switch SW shown in FIG. 3A or 3B is turned on, the logic circuit unit 5 receives the supply of the power supply voltage VDD from the branch line 20D, and the voltage of the virtual VSS line 30S ( VSSV) is used as a reference level for power and signals. This operation is performed in the entire MTCMOS circuit block 1 shown in FIG. At this time, since all the switches SW in the MTCMOS circuit block 1 are turned on, even if the on-resistance of each switch SW is several [Ω], the influence of the on-resistance can be ignored for the MTCMOS circuit block 1 as a whole. Ideally, VSSV = VSS.
On the other hand, in other circuit blocks sharing the actual power supply line pair (2D, 2S) as the global voltage line, the reference voltage VSS of the actual VDD line 2D is operated as the reference level of the power supply or signal.
Therefore, the state of power supply during normal operation is the same when MTCMOS is applied and when it is not applied.

In the present embodiment, a circuit cell (or switch cell) having a power supply IR drop (hereinafter referred to as a normal operation IR drop) _{Vd_rop_s} during operation of a circuit cell operating in the MTCMOS circuit block 1 and a switch in the MTCMOS circuit block 1. ) _Is estimated as IR drop (hereinafter referred to as return IR drop) _{Vd_rop_r} when the cell line including) returns from the stop to the start.
Then, an arrangement pitch n (referred to as switch arrangement pitch) n of the switches SW1 and SW2 that satisfies the condition that “the return IR drop V _{drop_r} is the normal operation IR drop V _{drop_s} is as follows” is obtained. Here, the “value of the switch arrangement pitch n” represents the arrangement interval of two cell lines including the switches SW1 and SW2 by the number of cell lines.

The above condition is that “the total value of the IR drop during normal operation in the MTCMOS circuit block operates normally without delay in the vicinity of the circuit cell in anticipation of potential fluctuations in the reference voltage line. If the power supply noise peak caused by the switch pair being turned on does not exceed the total value, there will be no delay effect on neighboring circuit cells. based on.
Or, “the total value of IR drop during normal operation in the MTCMOS circuit block can be regarded as VSSV = VSS during normal operation as described above. Therefore, the operation of the circuit cell that normally operates in the MTCMOS circuit block because MTCMOS is not applied. the size of the time in the premise that IR drop and equivalent "Compare the normal operation IR drop _{V Drop_s} a return IR drop _{V DROP_R} is for power fluctuations in the MTCMOS unapplied circuit cell, the power variation due to the turn-on of the MTCMOS switch Can also be taken.

  Under such an idea, it is considered to simultaneously control the switches SW in pairs. Then, on the condition that there is no other switch that is simultaneously controlled between the two switches, the appropriate range of the switch arrangement pitch n can be easily obtained by the method described below. Although the reason will be described later, when three or more simultaneously controlled switches are arranged at equal intervals, an appropriate range related to the switch arrangement pitch n is satisfied by any two adjacent switches among these switches. Thus, the power supply voltage fluctuation can be suppressed in the entire MTCMOS circuit block to such an extent that it does not affect the operation of neighboring circuit cells that are normally operating when the power switch is turned on.

FIG. 4 illustrates the relationship between two IR drops.
In the present embodiment, since the initial voltage of the virtual voltage line is the same when the stop time is the same, it is assumed that the peak value of the power supply noise shown in FIG. 4 is substantially determined by the return IR drop V drop — _r . Then, the return IR drop V drop — _r is compared with the normal operation IR drop V _d drop — s estimated in advance.
If the magnitude relationship between the two IR drops is as shown in FIG. 4A, it is necessary to change the way of switch connection. If it is as shown in FIG. 4B, the condition of the appropriate range is satisfied. Become.

<Placement and wiring method>
Based on the above concept, a placement and routing method including a switch connection method will be described. Here, it is assumed that one or both of the switch cell and the circuit cell having the switch are mixed in the MTCMOS application block and arranged in a line in the column direction. However, the placement and routing method is similarly applied when there is a cell line that does not include a switch between cell lines that include a switch.

FIG. 5 shows a schematic procedure from cell placement to wiring.
In step ST1, cell placement is performed by a normal method. At this time, the circuit cells including the switch SW may be arranged in a line in the column direction. As shown in FIG. 2, the arrangement area is preferably close to the arrangement area of the actual power supply line pair (2D, 2S), and if the arrangement space permits, the arrangement of the actual power supply line pair (2D, 2S) in the multilayer wiring structure is possible. A column column of circuit cells including the switch SW may be formed in the lower layer region of the metal layer.
Step ST2 is a step of calculating the switch arrangement pitch n, and includes finer steps ST21 to ST24.
Step ST21 relates to area division, and step ST22 relates to current calculation.

FIG. 6 illustrates the concept of area division and current calculation.
As shown in FIG. 6, in the MTCMOS circuit block 1, the power supply lines (actual power supply line pairs (2D, 2S)) connecting the cell lines have a plane pattern of parallel straps as shown in FIG. In this case, the strap interval, that is, the interval between the actual VDD lines 2D and the interval between the actual VSS lines 2S are the same.

The MTCMOS circuit block 1 can be divided into a fixed rectangular unit area composed of a wiring unit 2u and a cell line unit 1u.
The number of the unit areas in the MTCMOS circuit block 1 is defined as a reference unit “Square”. The reference unit “Square” is expressed by the following equation (1) using the number of cell lines N and the number of straps M representing the number of the actual VDD lines 2D and the actual VSS lines 2S.
[Equation 1]
“Square” = N × (M + 1) (1)

The reference unit “Square” is obtained in step ST21, and two currents are obtained in the next step ST22.
As shown in the following equation (2), the total operating current I _ope (current consumption) of the entire MTCMOS circuit block 1 is divided by the reference unit “Square” in the equation (1) to be normalized by the size of the unit area. operating current (hereinafter, the unit operating current) were _{I S} is found.
[Equation 2]
I _S = I _ope / Square (2)

Next, a drain current (hereinafter referred to as a switch current) I _ds flowing through one of the MTCMOS switches SW1 and SW2, for example, the switch SW1 as the first switch, when power is restored is obtained.
The switch current I _ds is determined in advance in consideration of a threshold voltage necessary for preventing leakage, a transistor size, process specifications, an area that can be arranged, and the like. Here, an NMOS transistor inserted between the virtual VSS line 30S and the branch line 20S is assumed, and the source-drain voltage is made uniform with the power supply voltage VDD. The source-drain voltage may be smaller than the power supply voltage VDD, such as using the average virtual VSS line 30S voltage at the time of recovery, but here the source-drain voltage is set to the power supply voltage for the most severe condition setting. It is assumed that it is equal to VDD.

In step ST23s of FIG. 5, the normal operation IR drop V drop _{— s} is calculated using the unit operating current I _S obtained in step ST22.

FIG. 7A shows an equivalent circuit of the area of interest during normal operation.
In FIG. 7A, a current source represents a total of an arbitrary number of logic circuit sections 5 (FIG. 3B) that allow a unit operating current _IS to flow in one unit area. The symbol “R” indicates the resistance of the current path from the local voltage line connection end of the current source to the branch line connection point of the wiring unit 2u belonging to the adjacent unit area, that is, a plurality of wiring resistances and contacts in the current path. This represents the total of the resistance of the part and its value.
The unit area number n shown in FIG. 7A is the required switch arrangement pitch n itself. In other words, when the switch SW1 as the first switch belongs to the unit area at one end, the second switch SW2 as the second switch exists in the unit area further ahead of the other end area. The number n of unit areas illustrated at the present time is unknown.

From this equivalent circuit, it is clear that the unit current flowing from the unit area at one end to which the switch SW1 belongs to the unit area of the switch SW2 is “I _S ”. Accordingly, IR drop in the unit area of the one end of the switch SW1 belongs is "RI _S". On the other hand, the unit currents flowing from the other (n−1) unit areas are also “I _S ”. Therefore, the current flowing out of the unit area adjacent to the one end (the second unit area from the bottom in FIG. 7A) is the current “I _S ” flowing from itself and the adjacent unit area to which the switch SW1 belongs. Since it is the sum of the flowing current “I _S ”, that is, “2I _S ”, the IR drop of the second unit area is “2RI _S ”.
Similarly, the IR drop of the third and subsequent unit areas is obtained by multiplying the total value of the current flowing out from the unit area and the current flowing out of all unit areas below the unit area in the figure by the resistance R, “3RI _S ”, “4 RI _S ”,..., “(N−1) RI _S ”, “nRI _S ”, respectively.
Therefore, as shown in the following equation (3-1), the normal operation IR drop V drop _{— s} is obtained as a total value of the n unit IR drops obtained as described above. Further, equation (3-1) is obtained from equation (3-1).

[Equation 3]
V _drop — s = RI _S +2 RI _S +...
_{+ (N-1) RI S} + nRI S ... (3-1)
V _drop — s = n (n + 1) RI _S / 2 (3-2)

In step ST23r of FIG. 5, the return IR drop V _{drop_r} is calculated using the switch current I _ds obtained in step ST22.

FIG. 7B shows an equivalent circuit of the attention area at the time of return.
In FIG. 7B, there is no current source because the circuit cell is in a stopped state. When the switch SW1 as the first switch receives a return command from a control unit (not shown) in the non-application circuit block 30 that is normally operating, the switch SW1 is turned on.
Then, as shown by a thick line in FIG. 7B, a large switch current _Ids flows through the n (unit) resistors R to the unit area to which the second switch SW2 as the second switch belongs, and then the circuit Sent outside the block.
Accordingly, the return IR drop V drop — _r when the switch current I _ds flows can be expressed as the following equation (4).
[Equation 4]
V _drop — _r = nRI _ds (4)

In step ST24 of FIG. 5, the two currents obtained by the expressions (3) and (4) are substituted into the IR drop relational expression (expression (5-1)) (expression (5-2)), and this is arranged. Then, a relational expression relating to the switch arrangement pitch n in Expression (5-3) is obtained.
[Equation 5]
V _{drop — s} ≧ V _{drop — r} (5-1)
n (n + 1) RI _S / 2 ≧ nRI _ds (5-2)
I _S / I _ds ≧ 2 / (n + 1) (5-3)

Equation (5-1) used here is an equation representing the conditions described in <Basic concept of placement and routing>, and the optimum range of switch placement pitch n satisfying this is obtained by Equation (5-3). I was able to.
Since Expression (5-3) is a ratio of known current values, if these current values are different, the optimum range of the switch arrangement pitch n is also changed accordingly.
If the control line connection target (switch pair) in step ST3 in FIG. 5 is selected so as to fall within the optimum range thus obtained, the condition described in <Basic concept of placement and routing> is satisfied. The generated power supply noise does not have a delay effect on the logic cell operation in the neighboring circuit block that is normally operating.

The above is a case where switches are selected in pairs, but this method can be applied as it is when three or more switches to be simultaneously controlled are arranged at equal intervals.
The reason is described below.

Here, it is assumed that n cell lines having a switch arrangement pitch n shown in FIG. 7A are set as one set and m sets are provided in the column direction.
The current during normal operation has flown through n cell lines in the discussion so far (one set). However, in the case of the above m sets, the current flows into mn pieces, so that the above equations (3-1) and (3) “N” in −2) may be simply replaced with “mn”, and the normal operation IR drop V drop _{— s} is _expressed by the following equations (6-1) and (6-2).

[Equation 6]
V _drop — s = RI _S +2 RI _S +...
+ (Mn-1) RI _S + mnRI _S (6-1)
V _drop — s = mn (mn + 1) RI _S / 2 (6-2)

On the other hand, one switch SW1 is turned on in the case of one set, but there are m switches SW1 in the case of m sets. For this reason, in the one end group (the first group) farthest from the current discharge side, “RI _ds ” flows when the internal switch SW1 is turned on, and the return IR drop V drop — _r is _expressed by the equation (4) described above. The same “nRI _ds ”.
In the second group, the sum of the current “RI _ds ” flowing from its own internal switch (SW1) and the current “RI _ds ” flowing from the first group, that is, “2RI _ds ” flows, and thereby the return IR drop V _{drop — r} is “2nRI _ds ”.
Similarly, the return IR drop of the third and subsequent sets is obtained by multiplying the total value of the current generated and flowing out of the set and the current flowing from all sets on one end side of the set by the resistance R, respectively. , “3nRI _S ”, “4 nRI _S ”,..., “(M−1) nRI _S ”, “mnRI _S ”.
Therefore, as shown in the following equation (7-1), the return IR drop V drop — _r is obtained as the total value of the m sets of return IR drops obtained as described above. Further, equation (7-1) is obtained from equation (7-1).

[Equation 7]
V _drop — _r = nRI _ds +2 nRI _ds +...
+ (M−1) nRI _ds + mnRI _ds (7-1)
V _drop — s = m (m + 1) nRI _ds / 2 (7-2)

Substituting the two currents found in Equation (6-2) and Equation (7-2) into the IR drop relational equation (Equation (8-1)) (Equation (8-2)) Then, a relational expression regarding the switch arrangement pitch n in Expression (8-3) is obtained.
[Equation 8]
V _{drop — s} ≧ V _{drop — r} (8-1)
mn (mn + 1) RI _S / 2 ≧ m (m + 1) nRI _ds / 2 (8-2)
I _S / I _ds ≧ (m + 1) / (mn + 1) (8-3)

  If the right side of this equation (8-3) is compared with the right side of the above equation (5-3) and “m” and “n” are unknown natural numbers, the following equation (9-1) holds: The switch arrangement pitch n may be determined only by the equation (5-3).

[Equation 9]
2 / (n + 1) ≧ (m + 1) / (mn + 1) (9-1)
(m−1) (n−1) ≧ 0 (9-2)

If the above formula (9-1) is rearranged, the above formula (9-2) is established.
Equation (9-2) holds in two cases: “m ≧ 1 and n ≧ 1” and “m ≦ 1 and n ≦ 1”, but “m” and “n” are natural numbers (≧ 1). In the former case, equation (9-2) always holds.
As described above, when three or more switches SW1 to be simultaneously controlled are arranged at equal intervals, if the above-described equation (5-3) is established for one of them, the number of switches SW1 (number of sets m) is independent. The power supply noise generated at the time of power recovery does not affect the delay of the logic cell operation in the neighboring circuit block that is normally operating.

FIG. 8A shows a control line connection example that can satisfy the optimum range of the above switch arrangement pitch as an example and a case where switches are connected to one control line in pairs.
In FIG. 8, the lines in the row direction collectively represent the branch line 20S and the virtual VSS line 30S. Further, the switch control unit (SW.CONT.) 31 shown in FIG. 8 is a circuit that always operates because it is actually provided in the non-application circuit block 30 of FIG.

First, when the voltage of the virtual VSS line 30S (VSSV) is close to the power supply voltage VDD, and by the source-drain voltage _V ds = VDD as the above-described method to obtain the switch current _{I ds,} obtained switch The current I _ds is substituted into the above equation (5-3).
Next, by changing the combination of the unit operating current I _S and the switch arrangement pitch n, so as to satisfy the equation (5-3), to determine the position of the switch pair to be controlled simultaneously.
This determination determines the position of the switch pair displayed as “Circle 1” in FIG.

FIG. 8B is a prediction diagram of the voltage (VSSV) of the virtual VSS line 30S at the time of switch control by the switch control unit 31. The initial switch-on time, the size of the switch, the resistance of the current path, etc. Next, the value V2 of the voltage (VSSV) at the time of switching on is determined. Since this voltage value V2 becomes the source / drain voltage V _ds of the switch, the switch current I _ds is greatly reduced at the second switch-on.
Therefore, even if the switch arrangement pitch n is small, the above-described conditions are satisfied. Generally, it is better that the switch pair is separated, so here, as indicated by “circle 2”, the second switch pair is set so that the maximum switch interval is obtained between the “circle 1” switch pairs. Deploy.
Since the voltage value of the third switch pair, the fourth switch pair (in this example, it becomes a fraction and a single switch) and the virtual VSS line 30S gradually decreases from V3 to V4, the optimum arrangement condition is gradually relaxed. Therefore, in the same manner, when switches are arranged sequentially from both sides toward the center of the switch arrangement, power supply noise is not affected by delay effects on neighboring circuit blocks in all switch controls. It becomes possible.

  When the combination of the switch pairs to be interconnected is determined in this way, the control lines CL1 to CL4 are wired to the switch control unit 31 as shown in the drawing so that the combination is realized. If connected to 31, the wiring step (ST3 in FIG. 5) ends.

According to this embodiment, the following benefits can be obtained.
Normally, in designing an MTCMOS application block, it is more efficient both in terms of area and TAT when a circuit that is powered off by an MTCMOS switch and a circuit that is always energized without being powered off are mounted together. It is.
However, there is a problem that power supply noise increases in the vicinity of the MTCMOS switch when power is restored.
In the present embodiment, even when the MTCMOS switch and the logic cell are arranged in the same cell line (for example, in the row direction), the MTCMOS switch can be controlled without affecting the circuit that is performing the normal operation when the power is restored.

It is a figure which shows an example of the layout of the semiconductor integrated circuit in connection with this embodiment. It is a figure which shows roughly the partial structure of the MTCMOS circuit block in connection with this embodiment. (A) And (B) is a figure which shows the example of arrangement | positioning in the cell of a switch. It is a figure which illustrates the relationship between two IR drops. It is a flowchart which shows the schematic procedure in connection with this embodiment from a cell arrangement | positioning to wiring. It is a figure which shows the view of area division and electric current calculation in connection with this embodiment. (A) is an equivalent circuit diagram of the area of interest during normal operation, and (B) is during return. (A) is a figure which shows the example of control line connection which can satisfy | fill the optimal range of switch arrangement pitch using the method of this embodiment. (B) is a figure which shows the voltage transition of a virtual VSS line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... MTCMOS circuit block, 2D ... Real VDD line (stem wiring), 2S ... Real VSS line (stem wiring), 3D ... Virtual VDD connection line, 3S ... Virtual VSS connection line, 20D, 20S ... Branch line, 30 ... Non Application circuit block, 30D ... virtual VDD line, 30S ... virtual VSS line, 31 ... switch control unit, 5 ... logic circuit unit, SW, SW1, SW2, SW3 ... switch, CL, CL1-CL4 ... control line

Claims (8)

Trunk wiring wired in one direction and applied with power supply voltage or reference voltage,
A plurality of branch lines each branched from a plurality of equally spaced main wiring locations in the one direction;
A local voltage line provided for each branch line, and at least one circuit cell connected to the local voltage line, each of at least one switch connected between the local voltage line and the branch line A plurality of cell lines whose arrangement (number and position) and non-arrangement are predetermined;
A plurality of control lines for connecting a predetermined number of the switches included in a plurality of cell lines separated from each other across one or more cell lines in the plurality of cell lines so as to be simultaneously controllable;
A semiconductor integrated circuit. The first and second switches of two cell lines that are simultaneously controlled by one control line are arranged at an equal distance from the main wiring at a pitch of the number of cell lines n (n: an integer of 2 or more). ,
When the first switch is turned on to activate the circuit cell, the nth cell line adjacent to the cell line including the second switch from the first cell line including the first switch on the first cell line side. In a plurality of circuit cells included up to the cell line, a potential drop (IR drop) generated in a current path from the first switch to a main wiring portion provided with a branch line connected to the second switch is The number of cell lines n is present for each cell line when a plurality of circuit cells are operated, and the number n of cell lines is less than or equal to the total value of n operating IR drops generated in the current path starting from each circuit cell. The semiconductor integrated circuit according to claim 1, which is determined. Between the two cell lines including the first and second switches arranged at a pitch of the cell line number n, the switches of the other cell lines are paired (however, when the fraction is rounded, they are not a pair but alone). Connected to other control lines,
When the circuit cell is activated, the first and second switches are turned on first, and the other control lines are controlled to be turned on in the order of decreasing the interval between two cell lines including a pair of switches. The semiconductor integrated circuit according to claim 2, further comprising: a switch control unit that performs switching. A plurality of cells in which a power supply voltage or a reference voltage applied to a trunk wiring wired in one direction is distributed through a plurality of branch lines each branched from a plurality of trunk wiring locations equally spaced in the one direction A method of arranging and wiring a semiconductor integrated circuit related to connection to a control line of a switch that controls connection between a local voltage line and a branch line connected to a circuit cell within a predetermined cell line with respect to a line,
Determining an arrangement pitch n (n: an integer of 2 or more) of two cell lines including two first and second switches controlled simultaneously by the control line;
Arranging and wiring the plurality of cell lines and the plurality of branch lines;
Arranging the trunk wiring in a direction orthogonal to the cell line and connecting to the plurality of branch lines;
An arrangement wiring step of at least one control line, wherein a plurality of switches are connected to one control line for simultaneous control in a plurality of cell lines where adjacent cell lines are separated by the arrangement pitch n or more; ,
Including
In the step of determining the wiring pitch n, when the first switch is turned on to activate the circuit cell, the first cell is changed from the first cell line including the first switch to the cell line including the second switch. In a plurality of circuit cells included up to the nth cell line adjacent on the line side, a potential drop generated in a current path from the first switch to a main wiring portion provided with a branch line connected to the second switch (IR drop) is present for each cell line when the plurality of circuit cells are operated, and is equal to or less than the total value of n operating IR drops generated in the current path starting from each circuit cell. The wiring pitch n is determined. A semiconductor integrated circuit placement and routing method. In the step of arranging and wiring the plurality of cell lines and the plurality of branch lines, each element of the branch lines and the local voltage lines, a circuit cell having a predetermined number of switches including the switch, the branch lines, The method for arranging and wiring a semiconductor integrated circuit according to claim 4, wherein each element of the local voltage line and a plurality of normal circuit cells each including a circuit are combined and arranged in a line. In the step of arranging and wiring the plurality of cell lines and the plurality of branch lines, a cell line including a circuit cell having the switch and a cell line without a switch in which the normal circuit cells are arranged in a line are predetermined. The placement and routing method for a semiconductor integrated circuit according to claim 5, wherein the placement is in the one direction by a rule. In the placement and routing step of the control line, when there is another cell line including a switch in addition to the first cell line within the placement pitch n, the switches in the other cell line can be controlled individually or simultaneously. Place and route other control lines to
5. A method for arranging and wiring a semiconductor integrated circuit according to claim 4. When arranging and wiring the other control lines, the control lines in the arrangement pitch n are sequentially connected to the switch pair that is farthest from each other while keeping the rules for connecting the control lines to the switch pair that is the farthest from each other. The placement and routing method for a semiconductor integrated circuit according to claim 7, wherein the placement and routing is repeated, and when a single switch that becomes a fraction remains at the end, a control line for controlling the single switch is placed and routed.

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