JPS5937736A - Current switching type logical circuit - Google Patents

Current switching type logical circuit

Info

Publication number
JPS5937736A
JPS5937736A JP57146174A JP14617482A JPS5937736A JP S5937736 A JPS5937736 A JP S5937736A JP 57146174 A JP57146174 A JP 57146174A JP 14617482 A JP14617482 A JP 14617482A JP S5937736 A JPS5937736 A JP S5937736A
Authority
JP
Japan
Prior art keywords
terminal
fets
fet
current switching
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57146174A
Other languages
Japanese (ja)
Inventor
Atsushi Takai
高井　厚志
Osamu Yumoto
湯本　攻
Shinya Sasaki
慎也 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57146174A priority Critical patent/JPS5937736A/en
Publication of JPS5937736A publication Critical patent/JPS5937736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To perform efficiently current switching, by turning on only the FET whose input voltage becomes higher than that of any other FET by greater than a specific value. CONSTITUTION:Drains of FETs F12...F1n are connected to a terminal 1, drains of FETs F21...F2n are connected to a terminal 2, and sources of the 1st and the 2nd FETs are connected in common to constitute a switch circuit part. Further, drains of FETs FS1...FSn are connected to the switch circuit part and sources are connected to a terminal 3. In this case, switching between the current switching FETs FS1...FSn, and FR2 connected to the terminal 3 is controlled by input voltages, respectively. When the voltage of one of inputs S1...Sn, and VR2 becomes higher than any other voltage by greater than the set value DELTAV, a current flows through the FET and others are turned off. Consequently, a constant current source is reduced to reduce electric power without reducing the speed.

Description

【発明の詳細な説明】 （１）発明の対象 本発明は、電界効果トランジスタまたはバイポーラトラ
ンジスタで構成される電流切換型論理回路に係り、特に
、全消費電力であり、さらに手選（以下余白） 択信号振幅駆動も可能とする、データ選択論理回路に関
する。DETAILED DESCRIPTION OF THE INVENTION (1) Object of the Invention The present invention relates to a current switching type logic circuit composed of field effect transistors or bipolar transistors, and particularly relates to a current switching type logic circuit that is configured with field effect transistors or bipolar transistors. The present invention relates to a data selection logic circuit that also enables selection signal amplitude driving.

（２）公知技術 第１図に、データ選択論理回路の論理図を示す。(2) Known technology FIG. 1 shows a logic diagram of a data selection logic circuit.

Ｄ１〜ｌ）ｎのｎ箇のデータ、入力であ）、８１〜Ｓｎ
がｎ箇の選択信号を示す。Ａ１〜Ａｎは論理積（ＡＮＤ
回路）、ＯＲは論理和（ＯＲ回路）を示す。データＤｉ
ｔ−選択するには、Ｓｉのみを＠１”とすることによシ
、Ａ１のみがＤｉ出力し他のＡは１０″′となシ、０几
の出力はＤｉとなる。これを、バイポーラトランジスタ
を用いたＣＭＬで実現したのが第２図である。ＯＲはワ
イアード論理和で実現している。D1-l) n data of n, input), 81-Sn
indicates n selection signals. A1 to An are logical products (AND
circuit), OR indicates a logical sum (OR circuit). Data Di
To select t-, only Si is set to @1'', only A1 outputs Di and the other A's output 10'', and the output of 0 becomes Di. FIG. 2 shows this realized by CML using bipolar transistors. OR is realized by wired logical sum.

これを、電界効果トランジスタ（以下ＦＥＴ）を用いた
電流切換型論理回路（以下ＢＣＭＬ：文献１参照）で実
現すると第３図となる。When this is realized by a current switching type logic circuit (hereinafter referred to as BCML: see Document 1) using field effect transistors (hereinafter referred to as FETs), the result is shown in FIG.

第２図または第３図の従来回路では、■１〜Ｉｎのｎ個
の定電流源を少なくとも必要とするため消費電力が大き
い欠点がめった。The conventional circuit shown in FIG. 2 or 3 requires at least n constant current sources of 1 to In, and therefore has the disadvantage of high power consumption.

（御　発明の目的 本発明は、速度を犠牲にすることなく、低消費電力で、
小振幅論理駆動することが可能なデータ選択回路を提供
することにある。(Object of the Invention) The present invention provides low power consumption without sacrificing speed.
The object of the present invention is to provide a data selection circuit capable of small amplitude logic driving.

（４）　　発明の詳細な説明 第２図および第３図の回路は第１図の論理を実現したも
のである。ところが第１図は、選択回路では入力８１〜
Ｓｎのどれか１つのみがｒｌＪという条件が有効に利用
されていない。この条件を利用することによシ、前述の
目的を達成することができる。(4) Detailed Description of the Invention The circuits shown in FIGS. 2 and 3 realize the logic shown in FIG. 1. However, in FIG. 1, the selection circuit has inputs 81 to 81.
The condition that only one of Sn is rlJ is not effectively utilized. By utilizing this condition, the above-mentioned purpose can be achieved.

（５）実施例とその効果 第４図に示す回路は、８１〜Ｓｎの多くともどれか１つ
が「１」である時のみ第３図と同じ論理動作をする。第
４図の回路は２つ以上のＳｉ　（ｉ＝１〜ｎ）が「１」
なる時出力は必ずしも確定しない欠点はあるが、データ
選択回路のようにＳｉのうち多くとも１つが「１」なる
条件下のもとでは、第３図と比較しても明らかなように
、定電流源１１〜Ｉｎ’！ｆ−１つの定電流源１１に減
らすことができる。この回路の速度は、電流電圧変換素
子Ｒ１または几２の出力端子１または２に接続される素
子によシ支配的に決定される。第３図と第４図において
は、ＦＥＴはＦ１１〜Ｆ１ｎとＦ２１〜Ｆ２ｎ、ＦＢＩ
、ＦＲ２と同じであるので速度も同じ程度である。(5) Embodiment and Effects The circuit shown in FIG. 4 performs the same logical operation as in FIG. 3 only when at least one of 81 to Sn is "1". In the circuit shown in Fig. 4, two or more Si (i=1 to n) are "1".
Although there is a drawback that the output is not necessarily fixed when the Current source 11~In'! It can be reduced to f-1 constant current source 11. The speed of this circuit is predominantly determined by the element connected to the output terminal 1 or 2 of the current-voltage conversion element R1 or 2. In Figures 3 and 4, the FETs are F11~F1n, F21~F2n, FBI
, and FR2, so the speed is also about the same.

第４図中の端子３に接続される電流切換用ＦＥＴ　ＦＳ
　１〜Ｆ　Ｓ　ｎとＦ’Ｒ，２１７）切換は、それぞれ
の入力電圧で制御される。それは、入力、８１〜５ｎＶ
Ｒ２のうち１つの電圧が他に比較して、ある設定値ΔＶ
よシ大きくなった時、そのＦＥＴに電流が導通し、他は
カットオフとなる。第２図〜第４図とも、入力Ｓ１〜５
ｎｔ−参照電圧Ｖ　ｌ（、２を用いてＶＲ２＋ΔＶまた
はＶ几２−ΔＶで論理動作させる。つまシ、振幅は２Δ
Ｖとなる。Current switching FET FS connected to terminal 3 in Figure 4
1 to F S n and F'R, 217) switching is controlled by the respective input voltages. It is input, 81~5nV
The voltage of one of R2 is a certain set value ΔV compared to the others.
When the FET becomes larger, current will be conducted to that FET and the others will be cut off. In both Figures 2 to 4, inputs S1 to 5
nt-reference voltage V l (, 2 is used to perform logic operation at VR2 + ΔV or V 几2 - ΔV. In other words, the amplitude is 2Δ
It becomes V.

データ選択回路の場合、８１〜Ｓｎは必ずいずレカが「
１」であるのでＦＲ２を電流が流れることはない。そこ
でＦＥＴ　　ＦＲ，２＝ｉ第５図の（ａ）から紛のよう
に省略することができる。この時、人力Ｓ１〜ｆ３ｎは
他よシΔＶだけ大きくなれば電流切換が可能なので振幅
はΔＶと第２図から第４図のものの２ΔＶよシ半分とな
シ、高速化が期待できる。In the case of a data selection circuit, 81 to Sn are always
1'', no current flows through FR2. Therefore, the FET FR,2=i can be conveniently omitted from FIG. 5(a). At this time, the current can be switched if the human power S1 to f3n is larger than others by ΔV, so the amplitude is half of ΔV and 2ΔV of those in FIGS. 2 to 4, and higher speed can be expected.

第６図は、さらに、データ入力をバランス入力としたも
ので、第４図に比べＤｉが必要であるが精度を要求され
る参照電圧ＶＲＩが省略できる。Further, in FIG. 6, the data input is a balanced input, and compared to FIG. 4, Di is required, but the reference voltage VRI, which requires accuracy, can be omitted.

また、電流切換型論理回路は一般にバランス出力なので
、Ｄ　ｉｆわざわざ作る必要はない。Furthermore, since current switching type logic circuits generally have balanced output, there is no need to create a Dif.

さらに、入力データが固定、または、ある選択信号の時
は固定出力をする場合データ電流切換ＦＥＴ　　Ｆ８ｉ
が省略できる。第７図（ａ）は第６図の一部を取り出し
たものであるが、入力データが「１」と固定の場合（ｂ
）のようにＦｌ量とＦ２１を省略して、ｐｓｉｉ端子１
に接続することによって同じ論理動作を行なう。Furthermore, if the input data is fixed or a certain selection signal is used, the data current switching FET F8i is used.
can be omitted. Figure 7 (a) is a partial extraction of Figure 6, but it shows the case where the input data is fixed at "1" (b
), omitting the Fl amount and F21, psii terminal 1
Perform the same logical operation by connecting to

（６）発明の効果 このように、定電流源を減らすことができ、速度をあま
シ犠牲にせずに電力を減らすことができる。さらに、第
６図のような応用では、参照電圧が必要もなく、参照電
圧発生回路を省略できる。(6) Effects of the invention In this way, the number of constant current sources can be reduced, and power can be reduced without sacrificing speed. Furthermore, in the application as shown in FIG. 6, there is no need for a reference voltage and the reference voltage generation circuit can be omitted.

固定データの出力には、データ電流切換ＦＥＴを省略で
きる。The data current switching FET can be omitted for outputting fixed data.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は選択回路の論理図。第２図および第３図は第１
図をＣＭＬ、電流切換型ＦＥＴ論理で実施した従来例を
示す。第４図〜第７図は、本発明の原理と実施例を示す
。 １．２・・・電流出力端子、几１．Ｒ２・・・電流電圧
変換素子、Ｄ１〜ｌ）ｎ・・・入力データ端子及び入力
電圧、Ｄ１〜］）ｎ・・・Ｄ１〜ｌ）ｎのコンプリメン
タリ、８１〜３ｎ・・・選択信号、ＶＲＩ、ＶＩＬ２・
・・参照電圧及び端子、Ｆｌ　１〜ＦＩ　ｎ、Ｆ２１〜
Ｆ２ｎ・・・データ電流切換用ＦＥＴ、ＦＳＩ〜ＦＳｎ
・・・デー預　１　図 Ａｒ 刃ｔ　　　　　　　　　　−−−−Ａ；スρｌ　　　　
　　　　　　　　力大　　　　　　　　　　　　吟、第
　４　図 、Ｓ／　　　　　　　　　　ハ　　　　　　　　−′１
１５　図 （ｇ、） 第　６　図 ４゜ η　γ　口 αすFIG. 1 is a logic diagram of the selection circuit. Figures 2 and 3 are
The figure shows a conventional example implemented using CML and current switching type FET logic. 4 to 7 illustrate the principles and embodiments of the invention. 1.2...Current output terminal, 几1. R2...Current-voltage conversion element, D1-l)n...Input data terminal and input voltage, D1-])n...D1-l)n complementary, 81-3n...Selection signal, VRI , VIL2・
・Reference voltage and terminal, Fl 1 ~ FI n, F21 ~
F2n...FET for data current switching, FSI~FSn
...Deposit 1 Figure Ar Blade t -----A; S ρl
Rikidaigin, Figure 4, S/Ha-'1
15 Figure (g,) Figure 6 4゜η γ Mouth α

Claims (1)

【特許請求の範囲】[Claims] １．２つの電流出力端子１，２と定電流回路に接続され
る端子３を有する論理回路において、ドレインが前記端
子ｌに接続された第１の以下ＦＥＴとドレインか前記端
子２に接続された第２のＦＥＴと、前記の第１のＦＥＴ
および第２のＦＥＴの各ソースを共通に接続したスイッ
チ回路部と、ドレインを前記スイッチ回路部に接続しソ
ースを前記端子３に接続した第３のＰＥＴとから構成さ
れる藏流切換型論ｆ１Ｍ回路。1. In a logic circuit having two current output terminals 1 and 2 and a terminal 3 connected to the constant current circuit, a first FET whose drain is connected to the terminal l and a drain connected to the terminal 2. a second FET and the first FET
and a switch circuit section in which the sources of the second FETs are connected in common, and a third PET whose drains are connected to the switch circuit section and sources are connected to the terminal 3. circuit.
JP57146174A 1982-08-25 1982-08-25 Current switching type logical circuit Pending JPS5937736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57146174A JPS5937736A (en) 1982-08-25 1982-08-25 Current switching type logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57146174A JPS5937736A (en) 1982-08-25 1982-08-25 Current switching type logical circuit

Publications (1)

Publication Number Publication Date
JPS5937736A true JPS5937736A (en) 1984-03-01

Family

ID=15401805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57146174A Pending JPS5937736A (en) 1982-08-25 1982-08-25 Current switching type logical circuit

Country Status (1)

Country Link
JP (1) JPS5937736A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107519A (en) * 1985-10-30 1987-05-18 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Logic circuit
US6307404B1 (en) * 1999-04-28 2001-10-23 Analog Devices, Inc. Gate structures with reduced propagation-delay variations

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107519A (en) * 1985-10-30 1987-05-18 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Logic circuit
US6307404B1 (en) * 1999-04-28 2001-10-23 Analog Devices, Inc. Gate structures with reduced propagation-delay variations

Similar Documents

Publication Publication Date Title
US4749886A (en) Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
JPH06244700A (en) Rectification type transmission gate circuit
JP2534346B2 (en) High-speed logic circuit
JPH09148913A (en) High potential difference level shift circuit
JPS5937736A (en) Current switching type logical circuit
JPH0876976A (en) Xor circuit, inversion selector circuit and adding circuit using these circuits
JPS625725A (en) Logical circuit for applying logical signal to control gate for switching fet
JPS61157115A (en) Cmos including 'chute through' current suppression means
JP3967248B2 (en) Level shift circuit
JPS61174814A (en) ECL output circuit
JPS6169212A (en) switching circuit
JPH0430765B2 (en)
KR960016142A (en) Variable delay circuit
JP3157056B2 (en) Full adder
JPS61186018A (en) Field effect transistor logic circuit
JP3038891B2 (en) Semiconductor integrated circuit device
JPH055700Y2 (en)
JPH0774620A (en) Buffer circuit
JPH06152381A (en) Input circuit
JP2570161B2 (en) Chip enable circuit
JPS59215124A (en) Cmos selecting circuit
JPH0377537B2 (en)
JPH07303040A (en) Logic circuit
JP2550942B2 (en) CMOS type logic integrated circuit
JPH0334723A (en) Gate array type semiconductor integrated circuit device