JPH1028046A - Multifunctional logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multifunctional logic circuit with a simple circuit configuration. SOLUTION: The middle point between resistors R1 and R1 having the same resistance is connected to the P1, N1, and N2 gates of a CMOS inverter. The size ratio between the P1 and N1 gates is set to, for example, 10:1 and the size of the P1 gate is made equal to those of the N2 and N3 gates of the inverter. When a control signal is 'L' and input signals A and B are respectively 'L' and 'H' (when the voltage at a point D is 1/2 Vcc), the output of the inverter becomes about Vcc, because the current flowing to the P1 gate becomes remarkably larger than that flowing to the N1 gate and the N3 gate is turned off. In other words, the threshold for operating the gates P1 to N3 become larger than the 112 Vcc as a whole. Therefore, the output of the inverter becomes 'H' and the logic of a multifunctional logic circuit becomes NAND logic. When the signal C is 'H' and the signals A and B are respectively 'L' and 'H', on the other hand, the output of the inverter becomes nearly the GND due to the characteristics and size ratio even when the gates N2, N3, and P1 are 'ON'. The threshold for operations becomes smaller than 112 Vcc as a whole. Therefore, the output of the inverter becomes 'L' and the logic of the logic circuit becomes NOR logic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit for outputting a signal of a predetermined potential (level) with respect to at least two input signals, and in particular, it is possible to change the logic of a signal output by a control signal. A multifunctional logic circuit. Such a multifunctional logic circuit has been found to reduce the size of a semiconductor device, and is required to be configured with a small space.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a conventional multifunctional logic circuit. FIG. 6A shows a case where one of NAND logic and NOR logic is selected, and FIG. By interposing an inverter, one logic is selected from the AND logic and the OR logic together with the NAND logic and the NOR logic.

As shown in FIG. 6A, a conventional multi-function logic circuit has a NAN to which input signals A and B are respectively inputted.
A control signal C is input together with a D circuit 11, a NOR circuit 12, and output signals D and E of these circuits 2:
1 selector (hereinafter, simply referred to as a selector) 13. According to this logic circuit, one of the output signal D from the NAND circuit 11 and the output signal E from the NOR circuit 12 can be selected by the control signal C input to the selector 13.

FIG. 6B shows an input of an output signal D (E) of the selector 13 in FIG. 6A and a signal F (G) obtained by inverting the output signal by an inverter 14 2: 1 selector (hereinafter simply referred to as selector) 15
Is provided, it is possible to further select the AND logic and the OR logic. For example, when the first-stage selector 13 selects the output signal D of the NAND circuit 11 by the control signal C, the second-stage selector 15 supplies the output signal D of the NAND circuit 11 and an AND logic that is inverted from the output signal D. Is input, and either one of them can be selected.

[0005] The selector 13 in the first stage is the NOR circuit 1
2 is selected, the second-stage selector 15
, An output signal E of the NOR circuit 12 and an output signal G as an OR logic, which is an inverted version of the output signal E, are input, and either one can be selected. That is, NA
It is possible to select one logic from ND logic, NOR logic, AND logic, and OR logic.

FIG. 7 shows the NAND circuit and the NO in FIG.
FIG. 3 is a circuit diagram showing an R circuit and a selector at an element level. FIG. 7A shows a NAND circuit 11, which includes a PMOS transistor P11 and an NMOS transistor N11 each having a gate to which a signal A is inputted, and an NMOS transistor N12 and a PMOS transistor P12 each having a gate to which a signal B is inputted. It is composed of

FIG. 7B shows a NOR circuit 12, which is a PMOS having a gate to which a signal A is input.
Transistor P13 and NMOS transistor N14
And a PMOS transistor P14 and an NMOS transistor N13 each having a gate to which the signal B is input. FIG. 7C shows the selector 13 (15).
The transmission TR11 receives the output signal D of the NAND circuit 11, the transmission TR12 receives the output signal E of the NOR circuit 12, and the inverter 16 receives the control signal C.

[0008]

The above-mentioned conventional multifunctional logic circuit includes a NAND circuit 11 and a NOR circuit 12 having a general configuration, and includes selectors 13 and 15 and an inverter 1.
4 realizes a multi-function capable of outputting various logics. In this case, as shown in FIG. 7, since the number of elements constituting the circuit increases, a space corresponding to the number of elements is naturally required.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to realize a multi-function capable of outputting various logics with a simple circuit configuration, thereby further miniaturizing a semiconductor device. .

[0010]

According to the present invention, there is provided a multifunctional logic circuit capable of generating output signals of different logics for at least two input signals. A pair of resistors R1 and R2 having the same resistance connected in series between A and B, and a pair of power sources Vc
PMOS transistors P1 and N connected between c and GND.
A pair of resistors R
C-MO in which the midpoint of R1 and R2 is connected to the gate respectively
An S-inverter IN1 and a middle point between the pair of resistors R1 and R2 are connected to a gate, and one electrode is connected to the C-inverter.
A MOS transistor N2 connected to the output of the MOS inverter IN1, a series connection of the MOS transistor N2, one electrode connected to a predetermined power supply GND, and a control signal for changing the logic of the output signal at the gate. Is input to a MOS transistor N3.

According to the multifunctional logic circuit of the present invention, since it can be simply constructed with a small number of elements,
The space can be reduced, and the size of the semiconductor device can be reduced.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A and 1B are diagrams for explaining a first embodiment of a multifunctional logic circuit according to the present invention. FIG. 1A is a circuit diagram, and FIG. 1B is a diagram showing each signal in the circuit of FIG. Is a truth table representing the levels of. FIG. 2 is a plan view showing only main components of the C-MOS inverter according to the first embodiment of the present invention.

This embodiment is a circuit which can select one of a NOR logic and a NAND logic. The circuit has an input signal A and an input signal B as shown in FIG.
And a pair of resistors R1 and R2 having the same resistance value connected between
And a C-MOS inverter IN1 comprising a PMOS transistor P1 and an NMOS transistor N1 each having an intermediate point between the pair of resistors R1 and R2 connected to a gate.
And

Further, the same signal as the input signal of the C-MOS inverter IN1 is input to the gate, and the source is connected to the C-MOS inverter IN1.
NMOS connected to the output of MOS inverter IN1
A transistor N2, an NMOS transistor N2 and a drain connected to each other, a source connected to the ground point GND, and a gate to which a control signal C is input;
It has a transistor N3.

FIG. 2 shows the C-MOS inverter IN1.
FIG. 2 is a plan view showing the structure of FIG. 1. A diffusion layer for forming an N-type or P-type region is provided on a semiconductor substrate (not shown), and a source electrode 2 and a drain electrode 3 of a PMOS transistor P1 are formed on these semiconductor layers. Widely formed, NM
Source electrode 4 and drain electrode 5 of OS transistor N1
Are formed with a width smaller than that of the PMOS transistor P1.

An oxide film (not shown) is formed on the source electrodes 2 and 4 and the drain electrodes 3 and 5, and the oxide film insulates the source electrodes 2, 4 and the drain electrodes 3 and 5 from each other. In this state, a common gate electrode 1 is formed in the upper layer. Also, a PMOS transistor P1 and an NMOS transistor
The drain electrodes 3 and 5 of the transistor N1 are electrically connected by forming a connection conductor 6 with a contact hole opened in the oxide film, and the source electrode 2 of the PMOS transistor P1 is connected to the power supply Vcc. NMOS
The source electrode 4 of the transistor N1 is connected to the ground point GND.

Note that the PMOS transistor P1 and the NMOS
The width of the transistor N1 differs depending on the width L of the gate electrode 1. For example, the width of the PMOS transistor P1 is set to 10 W with respect to the width W of the NMOS transistor N1.
And This is one condition for determining the operation threshold Vth of the C-MOS inverter IN1.
The width ratio is largely changed in order to reliably switch the output voltage level.

Although not shown, the NMOS transistors N2 and N3 have the same size as the PMOS transistor P1. First, a description will be given of a case where the level of the input signals A and B is changed by setting the control signal to the "L" (low) level in the multifunctional logic circuit as described above. The “L” level and “H” (high) level in the input signals A and B and the control signal C described below mean the ground GND level and the power supply Vcc level, respectively.

When the input signals A and B are both at "L" level, the level at the point D is also at "L" level, that is, C-MO.
The PMOS transistor P1 of the S inverter IN1 is turned on, the NMOS transistor N1 is turned off, and the NMOS transistor N1 is turned off.
Since the transistors N2 and N3 are also off, the output signal goes high at the level of the power supply Vcc. When one of the input signals A and B is at the “L” level and the other is at the “H” level, the resistances R1 and R2 are the same.
The level at point D becomes 1/2 Vcc by dividing the power supply Vcc.

In this case, the PMOS transistor P1 and the NMOS transistor N1 of the C-MOS inverter IN1
If both transistors are turned on, the size ratio of the two transistors is greatly changed to 10: 1 as shown in FIG. 2, so that the current flowing from the power supply Vcc in the PMOS transistor P1 to the output section is the same in the NMOS transistor N1. It is much larger than the current flowing from the output to the ground point GND.

When the control signal C is at "L" level, the NMOS transistors N2 and N3 are turned off, so that the output section is almost at the same level as the power supply Vcc. From the above results, the operating threshold value Vth as a whole of the C-MOS inverter and the NMOS transistors N2 and N3 for setting the output section to a predetermined level with respect to the voltage level at the point D
Is a value larger than 1/2 Vcc.

Therefore, the above condition, that is, when one of the input signals A and B is at the "H" level, the other is at the "L" level, the voltage at the point D is 1/2 Vcc, and the control signal C is at the "L" level As shown in FIG. 1B, the output signal goes to "H" level. Further, when both the input signals A and B become "H" level, the level at the point D becomes "H", the PMOS transistor P1 of the C-MOS inverter IN1 is turned off, the NMOS transistor N1 is turned on, and the NMOS transistor N1 is turned on. Since N2 and N3 are also off, the output signal becomes "L" level at the ground point GND level.

As described above, when the control signal is at "L" level, the output signals corresponding to the input signals A and B are NAND logic. Next, an operation when the level of the input signals A and B is changed by setting the control signal to the “H” level will be described. When the input signals A and B are both at the “L” level, the point D is at the “L” level and the CM
The PMOS transistor P1 of the OS inverter IN1 is turned on, the NMOS transistor N1 is turned off, and the NMOS transistor N1 is turned off.
Since the transistor N2 is also turned off, the output signal is
It goes to “H” level at the level of cc.

When one of the input signals A and B is at the "L" level and the other is at the "H" level, the resistance R1,
Since R2 is the same, point C is 1
/ 2Vcc. In this case, the C-MOS inverter IN
Assuming that both the PMOS transistor P1 and the NMOS transistor N1 are turned on, the control signal C is also at the "H" level, so that the NMOS transistors N2 and N3 are also turned on.

That is, the three NMOS transistors N1 to N3 on the ground point GND are turned on with respect to the PMOS transistor P1 on the power supply Vcc side. As described above, although the size of the NMOS transistor N1 is small, the size of the PMOS transistor P1 is equal to the size of the NMOS transistors N2 and N3. , Power supply V
output to ground GND rather than current flowing from cc to output
The current flowing through the output section is much larger, and the output section is almost at the same level as the ground point GND.

From the above results, the operating threshold value Vth as a whole of the C-MOS inverter and the NMOS transistors N2 and N3 for setting the output section to a predetermined level with respect to the voltage level at the point D is 1 / The value is smaller than 2 Vcc. Therefore, the above condition, that is, one of the input signals A and B is at the “H” level, the other is at the “L” level, and the voltage at the point D is 1 /
When 2Vcc and the control signal C are at "H" level, the output signal becomes "L" level as shown in FIG. 1B.

Further, when both the input signals A and B are at the "H" level, the level at the point D becomes "H" and the C-MOS
The PMOS transistor P1 of the inverter IN1 is turned off,
Since the NMOS transistor N1 is turned on and the NMOS transistors N2 and N3 are also turned on, the output signal goes low at the ground GND level. As described above, when the control signal is at the “H” level, the output signals for the input signals A and B have the NOR logic.

FIG. 3 is a circuit diagram for explaining a second embodiment of the multifunction logic circuit according to the present invention, and the same components as those in the first embodiment are denoted by the same reference numerals. This embodiment is different from the first embodiment in that a C-MOS inverter is provided at each of the input portions of the input signals A and B and the output portion, thereby preventing generation of an input current flowing between input terminals. The malfunction is prevented by bringing the voltage level of the output section closer to the level of the power supply Vcc and the ground point GND.

That is, in the preceding stage of the resistor R1, a C-type transistor comprising a PMOS transistor P2 and an NMOS transistor N4 is used.
The MOS inverter IN2 has a PMO
C-MOS inverters IN3 each including an S transistor P3 and an NMOS transistor N5 are provided,
Input signals A and B are input to gates, respectively. For example, when the input signal A is at the “H” level and the input signal B is at the “L” level, a current may flow from the terminal on the input signal A side to the terminal on the input signal B side. For example, since the input units include the C-MOS inverters IN2 and IN3, the current between the input terminals can be eliminated.

By the way, if a current flows between the input terminals, it affects an external circuit connected to the input terminal.
It may cause malfunction. On the other hand, also in the preceding stage of the output unit, the C-MOS inverter IN4 including the PMOS transistor P4 and the NMOS transistor N6 that input the output signal of the C-MOS inverter IN1 to the gate.
Is provided.

In the multi-function logic circuit of the first embodiment, as described above, the output section can generate the level of almost the power supply Vcc and the level of the ground point GND. A C-MOS inverter IN4 is provided, and a PMOS transistor P4 and an NMO
By reliably switching on and off with the S transistor N6, the output signal is set to the same level as the power supply Vcc and the ground point GND, thereby making the circuit operation more reliable.

However, in the case of the present embodiment, the output signal is inverted by the inverter IN4 of the output section, so that the logic is opposite to that of the first embodiment. 4A and 4B are diagrams for explaining a third embodiment of the multifunctional logic circuit according to the present invention. FIG. 4A is a circuit diagram, and FIG. 4B is a diagram illustrating each signal in the circuit of FIG. Is a truth table representing the levels of.

In this embodiment, as in the first embodiment, the input signal A
A pair of resistors R3 and R4 having the same resistance value, which connects between the gate and the input signal B, and a PMOS transistor P5 and an NMOS transistor N7 each having an intermediate point between the pair of resistors R3 and R4 connected to the gate. -MOS inverter IN5. Further, the C-MOS is connected to the gate.
The same signal as the input signal to the inverter IN5 is input,
A PMOS transistor P7 having a drain connected to the output of the C-MOS inverter IN5; a source and a drain of the PMOS transistor P7; a source connected to the power supply Vcc;
Is input to a PMOS transistor P6.

The CM in the first and second embodiments described above.
In the OS inverter IN1, the NMOS transistor N1
In contrast, the resistance of the PMOS transistor P1 is reduced by increasing the size of the PMOS transistor P1. On the other hand, the C-MOS inverter IN5 of the present embodiment has a PMO
NMOS transistor N7 for S transistor P5
Is increased, the resistance value of the NMOS transistor N7 is reduced. The size of each of the PMOS transistors P6 and P7 is made larger than that of the NMOS transistor N7 to reduce the resistance value.

First, an operation of the multi-function logic circuit when the control signal C is fixed at the "L" level will be described. When the input signals A and B are both at the "L" level, the level at the point D is also at the "L" level, and C-
The PMOS transistor P5 of the MOS inverter IN5 is turned on, the NMOS transistor N7 is turned off, and the PMO
Since the S transistors P6 and P7 are also turned on, the output signal goes to the level of the power supply Vcc, and goes to the "H" level as shown in FIG.

When one of the input signals A and B is at the "L" level and the other is at the "H" level, since the resistors R3 and R4 have the same value, the level at the point D is the power supply V.
cc is divided to 1/2 Vcc. In this case, C-MO
The PMOS transistors P5 and NM of the S inverter IN5
Even if both of the OS transistors N7 are turned on, the control signal C remains at "L" level and the power supply Vcc
Since the PMOS transistors P6 and N7 connected to the side are turned on, the output section is at the same level as the power supply Vcc.

From the above results, the operating threshold value Vth of the C-MOS inverter IN5 and the PMOS transistors P6 and P7 for setting the output portion to a predetermined level with respect to the voltage level at the point D is 1 It becomes a value larger than / 2Vcc. Accordingly, the above condition, that is, one of the input signals A and B is at the “H” level, the other is at the “L” level and the voltage at the point D is 1
/ Vcc and the control signal C is at "L" level, the output signal is at "H" level as shown in FIG.

Further, when the input signals A and B are both at the "H" level, the level at the point D becomes "H" and C-
The PMOS transistor P5 of the MOS inverter IN5 is turned off, the NMOS transistor N7 is turned on, and the PMO
Since the S transistor P7 is also off, the output signal is
It becomes “L” level at the ND level. As explained above,
When the control signal is at “L” level, the input signals A,
The output signal for B is NAND logic.

Next, the operation when the control signal C is fixed at the "H" level will be described. When the input signals A and B are both at the “L” level, the point D is at the “L” level and
A PMOS transistor P5 of the MOS inverter IN5
Turns on, the NMOS transistor N7 turns off, and PM
Since the OS transistor P6 is also turned off, the output signal becomes the "H" level as shown in FIG. 4B at the level of the power supply Vcc.

When one of the input signals A and B is at "L" level and the other is at "H" level, the resistance R3
Since R4 is the same, point D is 1 where power supply Vcc is divided.
/ 2Vcc. In this case, the C-MOS inverter IN
Assuming that both the PMOS transistor P5 and the NMOS transistor N7 are in the ON state,
Since the resistance of the transistor P5 is large, the current flowing from the output unit to the ground point GND via the NMOS transistor N7 is larger than the current flowing from the power supply Vcc side to the output unit.

Since the PMOS transistor P6 is turned off when the control signal C is at "H" level, the output section is substantially at the same level as the ground point GND. From the above results, the C-MOS inverter IN5 and the PMO for setting the output unit to a predetermined level with respect to the voltage level at the point D are shown.
The operating threshold value Vth of the S transistors P6 and P7 as a whole is smaller than 1/2 Vcc.

Therefore, the above condition, that is, when one of the input signals A and B is at the "H" level, the other is at the "L" level, the voltage at the point D is 1/2 Vcc, and the control signal C is at the "H" level As shown in FIG. 4B, the output signal goes to "L" level. Further, when the input signals A and B are both at the “H” level, the level at the point D becomes “H”,
A PMOS transistor P5 of the MOS inverter IN5
Turns off, the NMOS transistor N7 turns on, and PM
Since the OS transistors P6 and P7 are also turned off, the output signal becomes "L" level at the ground point GND level.

As described above, when the control signal is at "H" level, the output signals corresponding to the input signals A and B have NOR logic. Also in this embodiment, by providing the C-MOS inverter in each of the input unit and the output unit as described with reference to FIG. 3, the input current generated between the input terminals can be prevented, and the potential of the output signal can be reduced. The power supply Vcc level and the ground GND level can be reliably achieved.

FIG. 5 is a diagram for explaining a fourth embodiment of the multifunctional logic circuit according to the present invention. FIG. 5 (a) is a circuit diagram,
FIG. 5B is a truth table showing the level of each signal in this circuit. As in the first embodiment, the multifunction logic circuit according to the present embodiment includes a pair of resistors R5 and R6 having the same resistance value for connecting between the input signal A and the input signal B, and the pair of resistors R5 and R6.
PMO where the midpoint of R5 and R6 is connected to the gate respectively
It has a C-MOS inverter IN6 composed of an S transistor P8 and an NMOS transistor N8.

The control signal C is connected to the gate of the C-MOS inverter IN6 via the resistor R7. The resistor R7 has the same resistance value as the resistors R5 and R6 of the input section, and the configuration of the C-MOS inverter IN6 is such that the size ratio between the PMOS transistor P8 and the NMOS transistor N8 is, for example, about 2: 1. Thus, the operation threshold value Vth is set to about 1/2 Vcc.

In such a multifunctional logic circuit, each operation for an input signal when the control signal C is set to "L" level will be described first. When the input signals A and B are both at the “L” level, the level at the point D is also at the “L” level, that is, the PM level of the C-MOS inverter IN6.
OS transistor P8 is on, NMOS transistor N
8 is turned off and the output section is at the same level as the power supply Vcc, so that the output signal is at the "H" level.

When one of the input signals A and B is at the "L" level and the other is at the "H" level, the resistors R5 to R5
Since R7 has the same resistance value, from this relationship, the point D becomes 1/3 Vcc obtained by dividing the power supply Vcc into three equal parts. C-MO
The threshold value of the S inverter IN6 is 1 /
Since it is 2 Vcc, when the point D is 1/3 Vcc, it is regarded as "L" level, the PMOS transistor P8 is turned on, and N
Since the MOS transistor N8 is turned off, the output signal goes high.

Further, when both the input signals A and B are at the "H" level, the voltage at the point D becomes 2/3 Vcc due to the relationship between the resistors R5 to R7, and therefore the C-MOS inverter IN6
Becomes "H" level. Accordingly, since the PMOS transistor P8 is turned off and the NMOS transistor N8 is turned on, the output section is at the same level as the ground point GND, and the output signal is at the "L" level.

As described above, when the control signal is at the "L" level, the output signals corresponding to the input signals A and B are NAND logic. Next, an operation when the level of the input signals A and B is changed by setting the control signal to the “H” level will be described. When the input signals A and B are both at the "L" level, the point D becomes 1/3 Vcc due to the relationship between the resistors R5 and R7, and the level becomes "L" level for the C-MOS inverter IN6. Accordingly, the PMOS transistor P8 is turned on and the NMOS transistor N8 is turned off, so that the output signal goes high.

When one of the input signals A and B is at the "L" level and the other is at the "H" level, the voltage at the point D becomes 2/3 Vcc due to the relationship between the resistors R5 to R7. It goes to "H" level for MOS inverter IN6. Therefore, the PMOS transistor P8 is turned off,
Since the NMOS transistor N8 is turned on, the output signal goes to "L" level.

Further, when the input signals A and B are both at the "H" level, the level at the point D also becomes "H", and the C-MOS
The PMOS transistor P8 of the inverter IN6 is turned off,
Since the NMOS transistor N8 is turned on, the output signal goes to "L" level. As described above, when the control signal is at the “H” level, the output signals for the input signals A and B have the NOR logic.

Also in this embodiment, by providing a C-MOS inverter in each of the input section and the output section as described with reference to FIG. 3, the input current generated between the input terminals can be prevented and the output signal can be prevented. Can be reliably set to the power supply Vcc level and the ground GND level.
As described above, according to the fourth embodiment of the present invention, it is possible to realize a multifunctional logic circuit with an extremely simple configuration.

[0053]

According to the multifunctional logic circuit of the present invention, multifunctionalization can be realized with a small number of elements and a simple configuration, so that the space can be reduced.
This contributes to miniaturization of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a first embodiment of a multifunctional logic circuit according to the present invention.

FIG. 2 is a plan view of a C-MOS inverter unit according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining a second embodiment of the multifunctional logic circuit of the present invention.

FIG. 4 is a diagram for explaining a third embodiment of the multifunctional logic circuit of the present invention.

FIG. 5 is a diagram for explaining a fourth embodiment of the multifunction logic circuit according to the present invention.

FIG. 6 is a circuit diagram showing a conventional multifunctional logic circuit.

FIG. 7 is a circuit diagram showing each component of a conventional multifunction logic circuit at an element level.

Claims (6)

[Claims] 1. A multi-function logic circuit capable of generating output signals of different logics for at least two input signals, wherein the multi-function logic circuit has the same resistance value connected in series between two input terminals (A, B). A pair of resistors (R1, R2), a PMOS transistor (P1) and an NMOS transistor (N1) connected between a pair of power supplies (Vcc, GND), and a midpoint of the pair of resistors (R1, R2). Is connected to the gate of each of the C-MOS inverters (IN1)
A MOS transistor (N2) having a middle point connected to the gate of the pair of resistors (R1, R2) and one electrode connected to the output of the C-MOS inverter (IN1); A MOS transistor (N3) connected in series with the transistor (N2), one electrode of which is connected to a predetermined power supply (GND), and a gate to which a control signal for changing the logic of an output signal is input; Multifunctional logic circuit characterized by being performed. 2. The C-MOS inverter (IN1)
Are PMOS transistors (P1) in order to make the current of the PMOS transistor (P1) easier to flow than the NMOS transistor (N1).
The source electrode (2) and the drain electrode (3) of the transistor (P1) are formed larger than the same electrodes (4, 5) of the NMOS transistor (N1), and are connected to the output of the C-MOS inverter (IN1). An NMOS transistor (N2) having the same size as the PMOS transistor (P1) and having a gate connected to the middle point of the pair of resistors (R1, R2), between the point (GND), and the PMOS transistor (P1). 2. The multifunctional logic circuit according to claim 1, wherein an NMOS transistor (N3) having the same size and having a gate to which a control signal (C) for changing the logic of the output signal is input is connected in series. 3. The C-MOS inverter (IN5)
Is a PMOS transistor (N7) that is easier to flow than the PMOS transistor (P5).
Transistor (P5) and NMOS transistor (N7)
Of the C-MOS inverter (IN1) and a power supply (V
cc), a PMOS transistor having a larger electrode size than the transistors (P5, N7) constituting the C-MOS inverter (IN5) and having a gate connected to the middle point of the pair of resistors (R3, R4). (P7) and the P
2. A PMOS transistor (P6) having the same size as the MOS transistor (P7) and having a gate to which a control signal (C) for changing the logic of an output signal is input is connected in series. Multifunctional logic circuit. 4. A multi-function logic circuit capable of generating output signals of different logics for at least two input signals, wherein the multi-function logic circuit has the same resistance value connected in series between two input terminals (A, B). A pair of resistors (R5, R6), a PMOS transistor (P8) and an NMOS transistor (N8) connected between a pair of power supplies (Vcc, GND), and a midpoint of the pair of resistors (R5, R6). Is connected to the gate of each of the C-MOS inverters (IN6)
And a control signal (C) for changing the logic of the output signal.
Is connected to the C-MOS through a resistor (R7) having a predetermined resistance value.
A multifunctional logic circuit characterized by being configured to be input to an inverter (IN6). 5. The input terminal (A, B) according to claim 1, wherein
The C-MOS inverter (IN2, IN3) for inputting an input signal to a gate is provided at a front stage of a pair of resistors (R1, R2) connected in series between the inverters, respectively. Multifunctional logic circuit. 6. The output section of the C-MOS inverter (IN1) according to claim 1, wherein a potential of an output signal is supplied to a power supply (V).
6. The multi-function logic circuit according to claim 1, further comprising a C-MOS inverter (IN4) for setting any one of cc) level and ground (GND) level.