JPH0523547U - 電力半導体装置 - Google Patents

電力半導体装置

Info

Publication number
JPH0523547U
JPH0523547U JP071499U JP7149991U JPH0523547U JP H0523547 U JPH0523547 U JP H0523547U JP 071499 U JP071499 U JP 071499U JP 7149991 U JP7149991 U JP 7149991U JP H0523547 U JPH0523547 U JP H0523547U
Authority
JP
Japan
Prior art keywords
semiconductor element
mounting portion
solder
semiconductor device
element mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP071499U
Other languages
English (en)
Inventor
孝司 川久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP071499U priority Critical patent/JPH0523547U/ja
Publication of JPH0523547U publication Critical patent/JPH0523547U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

(57)【要約】 【目的】 半導体素子をリードフレームの半導体素子搭
載部にダイボンドする際に、ダイボンド用のハンダが半
導体素子のパッシベーションガラスにまで盛り上がるこ
と及び半導体素子搭載部と半導体素子との間のダイボン
ド用のハンダに気泡を巻き込むことを防止する。 【構成】 半導体素子１がボンディングされる半導体素
子搭載部１’を、該半導体素子搭載部１’周囲よりも上
位となるよう形成し、且つ半導体素子搭載部１’の表面
に、半導体素子１の端部に達する複数の溝９を設けてな
ることを特徴とする。

Description

【考案の詳細な説明】
【０００１】
【産業上の利用分野】
本考案は電力半導体装置に関する。
【０００２】
【従来の技術】
従来の技術について図７及び図８を参照して説明する。図７（ａ）は樹脂封止 前の電力半導体装置の平面図、図７（ｂ）は図７（ａ）のＡ−Ａ’線断面図、図 ８は図７（ｂ）のＰ部拡大図である。
【０００３】 従来の樹脂封止型の電力半導体装置の構造は、まず図７（ａ）及び（ｂ）の如 く、半導体素子１（トライアックチップ等）をリード端子２の載置片３にダイボ ンドし、端部にパッシベーションガラスの形成された半導体素子１と接続用リー ド端子４，４とをボンディングワイヤ５により内部結線し、回路形成する。
【０００４】 そして、リードフレーム６を封止樹脂でトランスファーモールド法により射出 成形し、樹脂封止後、タイバーを切断して電力半導体装置が完成する。
【０００５】
【考案が解決しようとする課題】
しかし、半導体素子１をリード端子２の載置片３にハンダ７でダイボンドする 場合、半導体素子１に形成されたパッシベーションガラス８に、ハンダ７が盛り 上がり半導体素子の耐圧不良が生じる場合があった。
【０００６】 また、半導体素子１とリードフレーム６の載置片３との間のハンダ７に気泡を 巻き込み安定なダイボンドができないという問題もあった。
【０００７】 そこで、本考案は、上記課題に鑑み、半導体素子のボンディングによる素子の 耐圧不良とハンダに気泡を巻き込んだボンディングを改善する電力半導体装置の 提供を目的とする。
【０００８】
【課題を解決するための手段】
前記目的を達成するために本考案は、リードフレームと、該リードフレームに ハンダによってボンディングされる半導体素子とを備え、前記半導体素子がボン ディングされる半導体素子搭載部を、該半導体素子搭載部周囲よりも上位となる よう形成し、且つ前記半導体素子搭載部の表面に、前記半導体素子搭載部端部に 達する複数の溝を設けてなることを特徴とする。
【０００９】
【作用】
半導体素子がボンディングされる半導体素子搭載部を、該半導体素子搭載部周 囲よりも上位となるよう形成し、且つ半導体素子搭載部の表面に、半導体素子搭 載部端部に達する複数の溝を設けてなるので、ハンダが半導体素子の端部のパッ シベーションガラスにまで盛り上がって付着するということはなく、しかも、ハ ンダに巻き込まれる気泡は溝を介して外部へ排出され確実なボンディングを行な えるので、高信頼性の半導体装置を実現できる。
【００１０】
【実施例】
本考案の一実施例について、図１乃至図４を参照して説明する。図１（ａ）は 本考案の一実施例による電力半導体装置の半導体素子搭載前の平面図、図１（ｂ ）は図１（ａ）のＢ−Ｂ’線断面図、図２は図１（ｂ）のＱ部拡大図、図３（ａ ）は本考案の一実施例による電力半導体装置の半導体素子搭載後の平面図、図３ （ｂ）は図３（ａ）のＢ−Ｂ’線断面図、図４は図３（ｂ）のＱ部拡大図である 。
【００１１】 なお、図７及び図８に示す従来例と同一機能部分には同一記号を付している。
【００１２】 本実施例による電力半導体装置は、リードフレーム６の載置片３の内、電力半 導体素子１の搭載部１’を、図１及び図２に示すように他の載置片３の面より高 位となるよう形成するとともに、搭載部１’の表面に複数の溝９を形成している 。
【００１３】 次に、上記のようなリードフレーム６の載置片３に対して、図３及び図４に示 すように半導体素子１をハンダ７でダイボンドし、半導体素子１とリード端子４ ，４とをボンディングワイヤ５により内部結線し回路形成する。
【００１４】 ここで、図４に示すように、半導体素子１が搭載される載置片３の半導体素子 １の搭載部１’を他の面より高位に形成しているため、ボンディング用に要され る以外の余分なハンダ７は下位の載置片に流れ、半導体素子１に形成されたパッ シベーションガラス８に盛り上がることは無い。
【００１５】 また、半導体素子１をボンディングする搭載部１’の表面に溝９を設けている ため、ダイボンド時にハンダ７に巻き込んだ気泡を溝９を介して外部へ逃がすこ とができる。
【００１６】 この時、前述のように搭載部１’を他の面より高位に形成しているので、その 断面図のハンダ７は薄く付着した状態であり、溝９に沿って外部に導出される気 泡は容易に排出される。
【００１７】 このように本実施例によれば、従来のように半導体素子のパッシベーションガ ラスにまでダイボンド用のハンダが盛り上がることなく、また搭載部と半導体素 子の間のダイボンド用ハンダに気泡を巻き込むこともないので高信頼性の半導体 装置を実現できる。
【００１８】 図５及び図６は本考案の他の実施例を示し、図５（ａ）は本実施例による電力 半導体装置の電力半導体素子搭載後の平面図、図５（ｂ）は図５（ａ）のＣ−Ｃ ’線断面図、図６は図５（ｂ）のＲ部拡大図である。
【００１９】 本実施例の電力半導体装置は図５及び図６に示すように、電力半導体素子１の 搭載部１’の周囲に凹部１０を形成するとともに、搭載部１’の表面に複数の溝 ９を形成している。
【００２０】 本実施例によっても、図１乃至図４の実施例と同様、半導体素子１のパッシベ ーションガラス８にまでダイボンド用のハンダ７が盛り上がること、及び搭載部 １’と半導体素子１の間のダイボンド用のハンダ７に気泡を巻き込むことを防止 でき高信頼性の半導体装置を実現できる。
【００２１】
【考案の効果】
以上説明したように本考案によれば、半導体素子をリードフレームの半導体素 子搭載部にダイボンドする際に、ダイボンド用のハンダが半導体素子のパッシベ ーションガラスにまで盛り上がること及び半導体素子搭載部と半導体素子との間 のダイボンド用のハンダに気泡を巻き込むことを防止でき、高信頼性の電力半導 体装置を実現できる。
【図面の簡単な説明】
【図１】（ａ）は本考案の一実施例による半導体装置の
半導体素子搭載前の平面図、（ｂ）は（ａ）のＢ−Ｂ’
線断面図である。
【図２】図１（ｂ）のＱ部拡大図である。
【図３】（ａ）は本考案の一実施例による半導体装置の
半導体素子搭載後の平面図、（ｂ）は（ａ）のＢ−Ｂ’
線断面図である。
【図４】図１（ｂ）のＱ部拡大図である。
【図５】（ａ）は本考案の他の実施例による半導体装置
の半導体素子搭載後の平面図、（ｂ）は（ａ）のＣ−
Ｃ’線断面図である。
【図６】図５（ｂ）のＲ部拡大図である。
【図７】（ａ）は従来例による半導体装置の半導体素子
搭載後の平面図、（ｂ）は（ａ）のＡ−Ａ’線断面図で
ある。
【図８】図７（ｂ）のＰ部拡大図である。
【符号の説明】
１ 半導体素子 １’半導体素子搭載部 ６ リードフレーム ７ ハンダ ９ 溝 １０ 凹部

Claims (1)

    【実用新案登録請求の範囲】
  1. 【請求項１】 リードフレームと、該リードフレームに
    ハンダによってボンデイングされる半導体素子とを備
    え、 前記半導体素子がボンディングされる半導体素子搭載部
    を、該半導体素子搭載部周囲よりも上位となるよう形成
    し、 且つ前記半導体素子搭載部の表面に、前記半導体素子搭
    載部端部に達する複数の溝を設けてなることを特徴とす
    る電力半導体装置。
JP071499U 1991-09-06 1991-09-06 電力半導体装置 Pending JPH0523547U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP071499U JPH0523547U (ja) 1991-09-06 1991-09-06 電力半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP071499U JPH0523547U (ja) 1991-09-06 1991-09-06 電力半導体装置

Publications (1)

Publication Number Publication Date
JPH0523547U true JPH0523547U (ja) 1993-03-26

Family

ID=13462428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP071499U Pending JPH0523547U (ja) 1991-09-06 1991-09-06 電力半導体装置

Country Status (1)

Country Link
JP (1) JPH0523547U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017099122A1 (ja) * 2015-12-11 2017-06-15 ローム株式会社 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017099122A1 (ja) * 2015-12-11 2017-06-15 ローム株式会社 半導体装置
JPWO2017099122A1 (ja) * 2015-12-11 2018-09-27 ローム株式会社 半導体装置
US10366905B2 (en) 2015-12-11 2019-07-30 Rohm Co., Ltd. Semiconductor device

Similar Documents

Publication Publication Date Title
US6707138B2 (en) Semiconductor device including metal strap electrically coupled between semiconductor die and metal leadframe
US6720642B1 (en) Flip chip in leaded molded package and method of manufacture thereof
KR100192028B1 (ko) 플라스틱 밀봉형 반도체 장치
US6242798B1 (en) Stacked bottom lead package in semiconductor devices
US20030143776A1 (en) Method of manufacturing an encapsulated integrated circuit package
KR960015827A (ko) 반도체 장치 및 그 제조방법
KR0178623B1 (ko) 반도체 장치
JP2000003988A (ja) リードフレームおよび半導体装置
US20040046267A1 (en) Semiconductor package having a die pad with downward extended tabs
JPH0523547U (ja) 電力半導体装置
JPS6086851A (ja) 樹脂封止型半導体装置
KR100220244B1 (ko) 솔더 범프를 이용한 스택 패키지
JP3395918B2 (ja) 半導体装置と半導体装置形成体及びその形成体の製造方法
JP2943769B2 (ja) 樹脂封止半導体装置
KR200154510Y1 (ko) 리드 온 칩 패키지
KR100252862B1 (ko) 반도체 패키지 및 그의 제조방법
JPH07101729B2 (ja) マルチチップ半導体装置およびその製造方法
JPH0294463A (ja) 半導体装置
KR200244924Y1 (ko) 반도체패키지
KR100475339B1 (ko) 리드프레임및그를이용한반도체칩패키지
JP2520612Y2 (ja) 樹脂封止型半導体装置
KR0119764Y1 (ko) 반도체 패키지
KR100345163B1 (ko) 볼 그리드 어레이 패키지
JPH02307233A (ja) 集積回路
CN112928033A (zh) 半导体裸片和夹用不同的连接方法制造半导体器件的方法