JPH0516173B2 - - Google Patents
Info
- Publication number
- JPH0516173B2 JPH0516173B2 JP57175071A JP17507182A JPH0516173B2 JP H0516173 B2 JPH0516173 B2 JP H0516173B2 JP 57175071 A JP57175071 A JP 57175071A JP 17507182 A JP17507182 A JP 17507182A JP H0516173 B2 JPH0516173 B2 JP H0516173B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- substrate
- film
- isolation region
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17507182A JPS5965445A (ja) | 1982-10-05 | 1982-10-05 | 半導体素子分離領域の形成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17507182A JPS5965445A (ja) | 1982-10-05 | 1982-10-05 | 半導体素子分離領域の形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5965445A JPS5965445A (ja) | 1984-04-13 |
JPH0516173B2 true JPH0516173B2 (enrdf_load_stackoverflow) | 1993-03-03 |
Family
ID=15989717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17507182A Granted JPS5965445A (ja) | 1982-10-05 | 1982-10-05 | 半導体素子分離領域の形成方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5965445A (enrdf_load_stackoverflow) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8401711A (nl) * | 1984-05-29 | 1985-12-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin plaatselijk een verzonken oxidelaag is aangebracht. |
JPH01315141A (ja) * | 1988-06-15 | 1989-12-20 | Toshiba Corp | 半導体装置の製造方法 |
US5260229A (en) * | 1991-08-30 | 1993-11-09 | Sgs-Thomson Microelectronics, Inc. | Method of forming isolated regions of oxide |
US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
EP0637074A3 (en) | 1993-07-30 | 1995-06-21 | Sgs Thomson Microelectronics | Process for the production of active and isolated areas by split imaging. |
US5977607A (en) * | 1994-09-12 | 1999-11-02 | Stmicroelectronics, Inc. | Method of forming isolated regions of oxide |
KR100197651B1 (ko) * | 1995-11-03 | 1999-06-15 | 김영환 | 반도체 소자의 소자 분리막 제조방법 |
US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
US5834360A (en) * | 1996-07-31 | 1998-11-10 | Stmicroelectronics, Inc. | Method of forming an improved planar isolation structure in an integrated circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4333964A (en) * | 1980-09-15 | 1982-06-08 | General Electric Company | Method of making integrated circuits |
-
1982
- 1982-10-05 JP JP17507182A patent/JPS5965445A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5965445A (ja) | 1984-04-13 |
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