JPH0511805B2 - - Google Patents

Info

Publication number
JPH0511805B2
JPH0511805B2 JP62302698A JP30269887A JPH0511805B2 JP H0511805 B2 JPH0511805 B2 JP H0511805B2 JP 62302698 A JP62302698 A JP 62302698A JP 30269887 A JP30269887 A JP 30269887A JP H0511805 B2 JPH0511805 B2 JP H0511805B2
Authority
JP
Japan
Prior art keywords
circuit
input
output
delay circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62302698A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01144719A (ja
Inventor
Shinji Fujii
Ikuo Tsucha
Kazuhiko Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP62302698A priority Critical patent/JPH01144719A/ja
Priority to DE8888119901T priority patent/DE3878180T2/de
Priority to US07/277,112 priority patent/US4994687A/en
Priority to EP88119901A priority patent/EP0318929B1/en
Priority to KR1019880015751A priority patent/KR910008514B1/ko
Publication of JPH01144719A publication Critical patent/JPH01144719A/ja
Publication of JPH0511805B2 publication Critical patent/JPH0511805B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03Astable circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/033Monostable circuits
JP62302698A 1987-11-30 1987-11-30 リトリガブル・マルチバイブレータ Granted JPH01144719A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62302698A JPH01144719A (ja) 1987-11-30 1987-11-30 リトリガブル・マルチバイブレータ
DE8888119901T DE3878180T2 (de) 1987-11-30 1988-11-29 Nachtriggerbarer multivibrator.
US07/277,112 US4994687A (en) 1987-11-30 1988-11-29 Retriggerable multivibrator
EP88119901A EP0318929B1 (en) 1987-11-30 1988-11-29 Retriggerable multivibrator
KR1019880015751A KR910008514B1 (ko) 1987-11-30 1988-11-29 재기동가능한 멀티바이브레이터

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62302698A JPH01144719A (ja) 1987-11-30 1987-11-30 リトリガブル・マルチバイブレータ

Publications (2)

Publication Number Publication Date
JPH01144719A JPH01144719A (ja) 1989-06-07
JPH0511805B2 true JPH0511805B2 (en, 2012) 1993-02-16

Family

ID=17912114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62302698A Granted JPH01144719A (ja) 1987-11-30 1987-11-30 リトリガブル・マルチバイブレータ

Country Status (5)

Country Link
US (1) US4994687A (en, 2012)
EP (1) EP0318929B1 (en, 2012)
JP (1) JPH01144719A (en, 2012)
KR (1) KR910008514B1 (en, 2012)
DE (1) DE3878180T2 (en, 2012)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059818A (en) * 1990-06-01 1991-10-22 Advanced Micro Devices, Inc. Self-regulating clock generator
US5124573A (en) * 1990-12-20 1992-06-23 International Business Machines Adjustable clock chopper/expander circuit
US5146121A (en) * 1991-10-24 1992-09-08 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5179303A (en) * 1991-10-24 1993-01-12 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
KR940005785B1 (ko) * 1991-12-31 1994-06-23 현대전자산업 주식회사 어드레스 전이 검출회로
US5359232A (en) * 1992-05-08 1994-10-25 Cyrix Corporation Clock multiplication circuit and method
US5331208A (en) * 1992-08-03 1994-07-19 Nvision, Inc. Non-retriggerable one-shot circuit
US5298799A (en) * 1992-12-31 1994-03-29 International Business Machines Corporation Single-shot circuit with fast reset
US5430399A (en) * 1993-04-19 1995-07-04 Sun Microsystems, Inc. Reset logic circuit and method
US5422585A (en) * 1993-09-24 1995-06-06 Fan Chiangi; Yung F. Apparatus for generating an output signal of a desired pulse width
JPH07202649A (ja) * 1993-12-27 1995-08-04 Toshiba Corp 逓倍回路
US5467037A (en) * 1994-11-21 1995-11-14 International Business Machines Corporation Reset generation circuit to reset self resetting CMOS circuits
JP3688392B2 (ja) * 1996-05-31 2005-08-24 三菱電機株式会社 波形整形装置およびクロック供給装置
JP3903588B2 (ja) * 1997-07-31 2007-04-11 ソニー株式会社 信号変化検出回路
US5986488A (en) * 1997-10-21 1999-11-16 Micron Technology, Inc. Method and apparatus for fast reset of a one-shot circuit
US5929684A (en) * 1998-03-06 1999-07-27 Siemens Aktiengesellschaft Feedback pulse generators
US20050195985A1 (en) * 1999-10-29 2005-09-08 American Technology Corporation Focused parametric array
JP2002370360A (ja) * 2001-06-15 2002-12-24 Canon Inc 記録ヘッド、その記録ヘッドを有するヘッドカートリッジ、その記録ヘッドを用いた記録装置、及び、記録ヘッド素子基板
CA2528588A1 (en) * 2003-06-09 2005-01-06 American Technology Corporation System and method for delivering audio-visual content along a customer waiting line
US7319355B2 (en) * 2006-01-03 2008-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Pulse generator
US7995778B2 (en) * 2006-08-04 2011-08-09 Bose Corporation Acoustic transducer array signal processing
US8130535B2 (en) * 2009-09-01 2012-03-06 Qualcomm Incorporated Flexible word-line pulsing for STT-MRAM
JP2012244389A (ja) * 2011-05-19 2012-12-10 New Japan Radio Co Ltd グリッジ処理回路
US9147620B2 (en) * 2012-03-28 2015-09-29 Teradyne, Inc. Edge triggered calibration
CN104658508B (zh) * 2015-03-24 2017-06-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735270A (en) * 1972-03-20 1973-05-22 Us Navy Delayed pulse generator
US3950654A (en) * 1974-11-14 1976-04-13 American Microsystems, Inc. Power-on initializing circuit for a calculator system
US3999085A (en) * 1975-07-14 1976-12-21 Stromberg-Carlson Corporation Noise rejection circuit
JPS5814622A (ja) * 1981-07-20 1983-01-27 Advantest Corp 遅延回路
JPS5940834A (ja) * 1982-08-28 1984-03-06 株式会社東芝 パルスx線診断装置
JPS59118135A (ja) * 1982-12-27 1984-07-07 株式会社東芝 X線診断装置
DE3324711C2 (de) * 1983-07-08 1986-07-24 Hewlett-Packard GmbH, 7030 Böblingen Impulsgenerator
US4741006A (en) * 1984-07-12 1988-04-26 Kabushiki Kaisha Toshiba Up/down counter device with reduced number of discrete circuit elements
US4623846A (en) * 1985-02-14 1986-11-18 Motorola, Inc. Constant duty cycle, frequency programmable clock generator
JPS6265300A (ja) * 1985-09-18 1987-03-24 Toshiba Corp 半導体記憶装置
US4710653A (en) * 1986-07-03 1987-12-01 Grumman Aerospace Corporation Edge detector circuit and oscillator using same
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US4760472A (en) * 1987-02-06 1988-07-26 Magnetic Peripherals Inc. Dual channel readback recovery system

Also Published As

Publication number Publication date
KR910008514B1 (ko) 1991-10-18
KR890009083A (ko) 1989-07-15
DE3878180D1 (de) 1993-03-18
EP0318929A3 (en) 1990-06-27
EP0318929B1 (en) 1993-02-03
JPH01144719A (ja) 1989-06-07
DE3878180T2 (de) 1993-05-27
US4994687A (en) 1991-02-19
EP0318929A2 (en) 1989-06-07

Similar Documents

Publication Publication Date Title
JPH0511805B2 (en, 2012)
US4641048A (en) Digital integrated circuit propagation delay time controller
KR920004335B1 (ko) 전압제어발진회로
US5736872A (en) Low voltage high speed phase frequency detector
US6320437B1 (en) Duty cycle regulator
US6844762B2 (en) Capacitive charge pump
EP0379169B1 (en) Signal delay circuit using charge pump circuit
US6831493B2 (en) Duty cycle regulator
US5959502A (en) Analog phase-locked loop including voltage regulator
US4596954A (en) Frequency doubler with fifty percent duty cycle output signal
JPH021620A (ja) 電圧制御発振回路
JPH04105411A (ja) 信号遅延回路、クロック信号発生回路及び集積回路システム
US4594563A (en) Signal comparison circuit and phase-locked-loop using same
US6853231B2 (en) Timing vernier using a delay locked loop
US5760655A (en) Stable frequency oscillator having two capacitors that are alternately charged and discharged
JPH01157612A (ja) 電圧制御発振回路
US5801568A (en) Precise delay line circuit with predetermined reset time limit
US6339345B1 (en) Semiconductor device equipped with output circuit adjusting duration of high and low levels
JP3455561B2 (ja) 信号遅延回路
JP3392278B2 (ja) 発振器
JPH06101677B2 (ja) タイマ−回路
JPH03102911A (ja) クロック信号発生回路
JP2918754B2 (ja) Pll回路
JPS6240819A (ja) しきい値電圧検出回路
JPS63226116A (ja) Pll回路

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees