JPH05102318A - Method and apparatus for forming conductive copper alloy plug - Google Patents
Method and apparatus for forming conductive copper alloy plugInfo
- Publication number
- JPH05102318A JPH05102318A JP4081500A JP8150092A JPH05102318A JP H05102318 A JPH05102318 A JP H05102318A JP 4081500 A JP4081500 A JP 4081500A JP 8150092 A JP8150092 A JP 8150092A JP H05102318 A JPH05102318 A JP H05102318A
- Authority
- JP
- Japan
- Prior art keywords
- copper alloy
- copper
- layer
- plug
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は銅合金導電プラグ形成方
法及び装置に関し、特に超大規模集積回路（ＶＬＳＩ）
金属相互接続構造、電気的導体、薄膜導電性ストライプ
及びそれらの製造方法について、こうした構造のための
銅合金導体に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for forming a copper alloy conductive plug, and more particularly to a very large scale integrated circuit (VLSI).
Metal interconnect structures, electrical conductors, thin film conductive stripes and methods of making them are suitable for copper alloy conductors for such structures.
【０００２】[0002]
【従来の技術】過去のＶＬＳＩ製造ステツプにおいて
は、単一の基板上に配置された半導体領域又は半導体デ
バイス内におけるコンタクト及び相互接続のための単一
の合金材料としてアルミニウムが使用されていた。アル
ミニウムは低コスト、優れたオーミツクコンタクト及び
高導電率をもつているので好ましい。しかしながら純粋
なアルミニウム薄膜導電性ストライプは、融点が低いた
めにその使用が低温処理に制限され、コンタクト及び接
続不良の原因になるアニール時にシリコン内に拡散した
り、エレクトロニクス・マイグレーシヨンをしたりする
など望ましくない特性をもつている。その結果、純粋な
アルミニウム以上の利点を有する多数のアルミニウム合
金が開発された。例えば米国特許第 4,566,177号におい
ては、エレクトロ・マイグレーシヨン抵抗を改良するた
めに合計で重量比３〔％〕までのシリコン、銅、ニツケ
ル、クロム及び又はマンガンを含有するアルミニウム合
金の導電層が開発された。米国特許第 3,631,304号にお
いてはエレクトロ・マイグレーシヨンを改良するために
アルミニウム及び酸化アルミニウムの合金が作られた。BACKGROUND OF THE INVENTION In the past VLSI manufacturing steps, aluminum was used as the sole alloy material for contacts and interconnects in semiconductor regions or semiconductor devices located on a single substrate. Aluminum is preferred because of its low cost, excellent ohmic contact and high conductivity. However, pure aluminum thin film conductive stripes have a low melting point that limits their use to low temperature processing, such as diffusion into silicon during annealing, which causes contact and connection failures, and electronics migration. Has undesired properties. As a result, numerous aluminum alloys have been developed that have advantages over pure aluminum. For example, in U.S. Pat. No. 4,566,177, a conductive layer of an aluminum alloy containing a total of up to 3% by weight of silicon, copper, nickel, chromium and / or manganese has been developed to improve electromigration resistance. It was In U.S. Pat. No. 3,631,304 alloys of aluminum and aluminum oxide were made to improve electromigration.
【０００３】現在のＶＬＳＩ技術は、将来のＶＬＳＩデ
バイスで必要とされる高回路密度及び一段と速い動作速
度から生ずるバツクエンド・オブ・ザ・ライン（ＢＥＯ
Ｌ）配線要求をきびしく要求した。このことは、導電ラ
インをますます小さくしながら一段と高い電流密度を実
現することを要求する。かくして、一段と高いコンダク
タンスを有する配線が必要となり、一段と大きな配線断
面積を有するアルミニウム合金導体又は一段と高いコン
ダクタンスを有する配線材料が必要となつた。産業界に
おける傾向は、銅のコンダクタンスがアルミニユウムの
コンダクタンスよりも大きいので純粋な銅を用いて高コ
ンダクタンス配線材料を開発することである。Current VLSI technology results from the back end of the line (BEO) resulting from the high circuit densities and faster operating speeds required in future VLSI devices.
L) The wiring requirement was severely requested. This requires achieving even higher current densities while making conductive lines smaller and smaller. Thus, a wiring having an even higher conductance is required, and an aluminum alloy conductor having an even larger wiring cross-sectional area or a wiring material having an even higher conductance is required. The trend in the industry is to develop high conductance wiring materials using pure copper because the conductance of copper is greater than that of aluminum.
【０００４】[0004]
【発明が解決しようとする課題】ＶＬＳＩ相互接続構造
の形成においては、銅がライン、バイア、又は他の凹所
内に堆積されることにより、同一基板上の半導体領域又
は半導体デバイスを相互接続する。銅は半導体デバイス
接合において幾つかの難点の原因として知られており、
銅がシリコン基板内に拡散すれば、これがデバイスの機
能不全の原因となり得る。さらに純粋な銅は二酸化ケイ
素及びポリイミドのような酸素を含む絶縁体への接着が
良くない。かくしてＢＥＯＬ銅金属処理のための現在の
手段は、1000〔Å〕以上もの厚さを有する拡散障壁及び
又は接着層を含む。例えば、ＶＬＳＩ相互接続構造１０
の一部の概略を図５に示す。構造１０において、銅プラ
グ１２はＶＬＳＩデバイス内に配設された導電層及び半
導体素子を相互接続するために用いられる。銅導電ライ
ン１８の表面に置かれた絶縁層１６に凹所１４が形成さ
れる。物理蒸着法又は化学蒸着法を用いて、相互接続構
造１０を接着層２０及び銅プラグ１２で埋める。銅は酸
素を含む絶縁体にも銅自身にも十分に接着しないので、
接着剤として接着層２０を使用することにより銅プラグ
１２を絶縁層１６及び銅導電ライン１８に接着させるこ
とができる。接着層２０はチタン−タングステン（Ｔｉ
Ｗ）又はチタン−チツ化物（ＴｉＮ）のような耐火性金
属複合体からなる。In forming VLSI interconnect structures, copper is deposited in lines, vias, or other recesses to interconnect semiconductor regions or devices on the same substrate. Copper is known to be the cause of some difficulties in joining semiconductor devices,
If copper diffuses into the silicon substrate, this can cause device malfunction. Furthermore, pure copper does not adhere well to insulators containing oxygen such as silicon dioxide and polyimide. Thus, current means for BEOL copper metal processing include diffusion barriers and / or adhesion layers having a thickness of 1000 [Å] or more. For example, VLSI interconnect structure 10
An outline of a part of the above is shown in FIG. In structure 10, copper plugs 12 are used to interconnect conductive layers and semiconductor elements disposed within VLSI devices. A recess 14 is formed in the insulating layer 16 located on the surface of the copper conductive line 18. The interconnect structure 10 is filled with an adhesive layer 20 and a copper plug 12 using physical vapor deposition or chemical vapor deposition. Since copper does not adhere well to the oxygen-containing insulator and to the copper itself,
The copper plug 12 can be bonded to the insulating layer 16 and the copper conductive line 18 by using the adhesive layer 20 as an adhesive. The adhesive layer 20 is made of titanium-tungsten (Ti
W) or a refractory metal composite such as titanium-titide (TiN).
【０００５】他のＶＬＳＩ相互接続構造２２の一部の概
略を図６に示す。相互接続構造２２内の銅プラグ１２
は、シリコン基板２６内に形成された半導体領域２４と
コンタクトするために使用される。図示のように領域２
４はケイ化タンタル（ＴａＳｉ2 ）又はケイ化コバルト
（ＣｏＳｉ2 ）からなるケイ化金属コンタクトになる。
銅は低温において容易にケイ化物と反応してシリコン基
板２６内に拡散するので、拡散障壁及び接着層２０がこ
うした拡散を阻止し、銅プラグ１２が絶縁層１６に接着
できるようにするために用いられる。A schematic of a portion of another VLSI interconnect structure 22 is shown in FIG. Copper plug 12 in interconnect structure 22
Are used to contact the semiconductor regions 24 formed in the silicon substrate 26. Area 2 as shown
4 is a metal silicide contact made of tantalum silicide (TaSi 2 ) or cobalt silicide (CoSi 2 ).
Since copper readily reacts with silicide at low temperatures and diffuses into the silicon substrate 26, diffusion barrier and adhesion layer 20 is used to prevent such diffusion and allow copper plug 12 to adhere to insulating layer 16. Be done.
【０００６】接着層２０のような拡散障壁及び又は接着
層をＢＥＯＬ銅金属処理に使用すると、幾つかの問題点
が生ずる。構造１０において接着層２０は、凹所１４を
部分的に被覆することによつて銅導電体１２及び銅導電
ライン１８間に１つの層を挿入する。これは接触抵抗を
上昇させる上に、接着層２０の抵抗を直列に付加する。
構造１０及び構造２２において拡散障壁及び又は接着層
２０は、導電性ではあるが、純粋な銅よりも抵抗が大き
い上に、その存在は凹所１４の銅の断面積を減少させる
ので、ミクロン以下であるラインの電流導通能力を低減
させる。かくしてＢＥＯＬ配線に必要とされる電流需要
を満たすために、上述の問題点を含まない銅金属処理を
開発する必要がある。The use of diffusion barriers and / or adhesive layers, such as adhesive layer 20, in BEOL copper metal processing presents several problems. In structure 10, adhesive layer 20 inserts a layer between copper conductor 12 and copper conductive line 18 by partially covering recess 14. This not only increases the contact resistance, but also adds the resistance of the adhesive layer 20 in series.
In structures 10 and 22, the diffusion barrier and / or adhesion layer 20 is electrically conductive, but more resistive than pure copper, and its presence reduces the copper cross-sectional area of the recess 14 so that it is submicron. To reduce the current carrying capability of the line. Thus, in order to meet the current demands required for BEOL wiring, there is a need to develop a copper metallization that does not include the above-mentioned problems.
【０００７】本発明はＶＬＳＩ相互接続構造内に銅合金
によりバイア、ライン、及び他の凹所を設け、堆積した
合金の表面及び酸素含有絶縁体に接触している合金の表
面に合金元素酸化物の薄い層を形成する方法を提案す
る。また本発明は本発明の方法を用いて形成される新規
なＶＬＳＩ相互接続構造を提案する。The present invention provides vias, lines, and other recesses in copper alloys in VLSI interconnect structures, with alloying element oxides on the surface of the deposited alloy and on the surface of the alloy in contact with the oxygen-containing insulator. We propose a method to form a thin layer of. The present invention also proposes a novel VLSI interconnect structure formed using the method of the present invention.
【０００８】本発明は従来技術による拡散障壁及び又は
接着層を使用するＢＥＯＬ銅金属処理を大幅に改善する
ものである。従来技術は２つの堆積ステツプを必要とす
るが、本発明による方法の一実施例においては１つの堆
積ステツプのみを必要とする。第２に本発明は、バイ
ア、ライン又は凹所において利用し得る銅合金の断面積
を増大させることによつて、ミクロン以下であるライン
の電流導通能力を向上させる。最後に本発明は、半導体
素子又は導電層を相互に接続する相互接続構造において
使用される従来技術の接着層に存在する直列抵抗及び接
触抵抗を除去する。The present invention represents a significant improvement over the BEOL copper metallurgical process using diffusion barriers and / or adhesion layers of the prior art. Whereas the prior art requires two deposition steps, in one embodiment of the method according to the invention only one deposition step is required. Second, the present invention improves the current carrying capability of submicron lines by increasing the cross-sectional area of the copper alloy available in vias, lines or recesses. Finally, the present invention eliminates series resistance and contact resistance present in prior art adhesive layers used in interconnect structures that interconnect semiconductor devices or conductive layers.
【０００９】[0009]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、基板の１つの主要な平面上に配置
された酸素含有絶縁体層１６内に形成されたＶＬＳＩ相
互接続構造２８の凹所１４内に銅合金導電プラグ３０を
形成する方法において、銅及び原子百分率 2.0〔％〕未
満の合金元素からなる銅合金を形成するステツプと、相
互接続構造２８の凹所１４内に銅合金を堆積させると共
に、銅合金プラグ３０並びにプラグの露出している表面
及びプラグの酸素含有絶縁体１６に接触している面に合
金元素の酸化物の薄膜層３２を形成するステツプとを含
むようにする。SUMMARY OF THE INVENTION To solve this problem, the present invention provides a recess for a VLSI interconnect structure 28 formed in an oxygen-containing insulator layer 16 disposed on one major plane of a substrate. In the method of forming the copper alloy conductive plug 30 in the place 14, a step of forming a copper alloy containing copper and an alloy element having an atomic percentage of less than 2.0 [%] and a copper alloy in the recess 14 of the interconnection structure 28 are formed. Depositing and including a copper alloy plug 30 and a step of forming a thin film layer 32 of an alloying element oxide on the exposed surface of the plug and on the surface of the plug in contact with the oxygen-containing insulator 16. ..
【００１０】[0010]
【作用】本発明の方法の第１ステツプは、原子百分率
2.0〔％〕未満の合金元素を含む銅合金を形成すること
である。本発明の一実施例における第２すなわち最終ス
テツプは、薄い酸化物層を形成するのに適した堆積温度
によりバイア、ライン又は凹所内に銅合金を堆積させる
ことである。当該銅合金は物理蒸着（ＰＶＤ）法又は化
学蒸着（ＣＶＤ）法のいずれかによつて堆積させること
ができる。本発明の他の実施例の第２ステツプにおいて
は、薄膜酸化物層を形成しない堆積温度によりバイア、
ライン又は凹所内に銅合金を堆積させる。次に、相互接
続構造がアニール処理されて薄膜酸化物層が形成され
る。The first step of the method of the present invention is the atomic percentage.
A copper alloy containing less than 2.0% of alloying elements is formed. The second or final step in one embodiment of the invention is to deposit the copper alloy in the vias, lines or recesses with a deposition temperature suitable to form a thin oxide layer. The copper alloy can be deposited by either physical vapor deposition (PVD) or chemical vapor deposition (CVD). In a second step of another embodiment of the present invention, the vias are deposited at a deposition temperature that does not form a thin oxide layer.
Deposit copper alloy in the line or recess. The interconnect structure is then annealed to form a thin film oxide layer.
【００１１】当該酸化物層は幾つもの機能を果たす。第
１に、当該酸化物層は接着剤として作用することによ
り、銅合金が酸素含有絶縁体に接着できるようにする。
第２の機能としてこの酸化物層は拡散障壁として作用
し、これによつてラインすなわち凹所内に銅合金を封じ
込める。第３の機能としてこの酸化物層は表面保護層と
して作用し、これによつて堆積した銅合金に耐食性を与
える。最後に、この酸化物層は小丘の形成を防止する。The oxide layer serves several functions. First, the oxide layer acts as an adhesive, allowing the copper alloy to adhere to the oxygen-containing insulator.
As a second function, this oxide layer acts as a diffusion barrier, thereby containing the copper alloy in the line or recess. As a third function, this oxide layer acts as a surface protective layer, thereby providing corrosion resistance to the deposited copper alloy. Finally, this oxide layer prevents the formation of mounds.
【００１２】[0012]
【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.
【００１３】図面中の同一の参照番号は同一の構成要素
を示す。Like reference numerals in the drawings indicate like elements.
【００１４】本発明に従つて、酸素含有絶縁体層内のバ
イア、ライン又は他の凹所内に銅及び合金元素からなる
銅合金を堆積させ、当該銅合金上に合金元素の酸化物層
を形成することにより拡散障壁層及び自己保護層として
用いることによつて、新規な相互接続構造が形成され
る。図１は、銅合金プラグ３０及び合金元素の酸化物層
３２を有するＶＬＳＩ相互接続構造２８の一部にあるラ
イン又は凹所の断面の概略図である（図解の便宜をはか
る目的で凹所１４をバイアと呼ぶが、この凹所１４はラ
イン又は他の相互接続用の凹所であつても良い）。In accordance with the present invention, a copper alloy of copper and alloying elements is deposited in vias, lines or other recesses in the oxygen-containing insulator layer to form an alloying element oxide layer on the copper alloy. By using it as a diffusion barrier layer and a self-protection layer, a novel interconnection structure is formed. FIG. 1 is a schematic view of a cross section of a line or recess in a portion of a VLSI interconnect structure 28 having a copper alloy plug 30 and an oxide layer 32 of an alloying element (recess 14 for convenience of illustration). Is called a via, but this recess 14 may be a recess for lines or other interconnections).
【００１５】相互接続構造はＶＬＳＩデバイスの一部分
であり、金属で充填された凹所を用いてＶＬＳＩデバイ
ス上の半導体領域、素子又は導電層を相互に接続する。
図１に示すように、相互接続構造２８は銅導電ライン１
８を含む。絶縁層１６は導電ライン上に形成され、その
中に周知のフオトリソグラフイ技術及びエツチング技術
によつて形成されたバイア１４を含む。バイア１４の幅
は一般的には１〔μｍ〕又はそれ以下の程度の大きさで
ある。例えば絶縁層１６は二酸化ケイ素又はポリイミド
からなる酸素含有物質である。バイア１４は絶縁層１６
及び銅導電ライン１８上に形成されるコンタクト又はラ
イン間に導電性接続を実現する手段である。The interconnect structure is part of the VLSI device and uses metal filled recesses to interconnect the semiconductor regions, elements or conductive layers on the VLSI device.
As shown in FIG. 1, the interconnect structure 28 includes copper conductive lines 1
Including 8. Insulating layer 16 is formed over the conductive lines and includes therein vias 14 formed by well-known photolithographic and etching techniques. The width of the via 14 is generally about 1 [μm] or less. For example, the insulating layer 16 is an oxygen-containing substance made of silicon dioxide or polyimide. The via 14 is an insulating layer 16
And a means for achieving a conductive connection between contacts or lines formed on the copper conductive lines 18.
【００１６】本発明の第１ステツプは、原子百分率 2.0
〔％〕以下に抑えた合金元素を含む銅合金を形成するこ
とである。当該合金は標準的な冶金合金技術によつて形
成される。当該合金銅のエレクトロマイグレーシヨン抵
抗は純粋な銅のエレクトロマイグレーシヨン抵抗と同様
である。本発明の方法のための銅合金の形成に使用し得
る適正な合金元素にはアルミニウム及びクロムが含まれ
る。The first step of the present invention is to have an atomic percentage of 2.0.
[%] Is to form a copper alloy containing an alloy element suppressed below. The alloy is formed by standard metallurgical alloying techniques. The electromigration resistance of the alloy copper is similar to the electromigration resistance of pure copper. Suitable alloying elements that can be used to form copper alloys for the method of the present invention include aluminum and chromium.
【００１７】図２において本発明の一実施例における第
２ステツプは、蒸着又はスパツタリングなどの物理蒸着
（ＰＶＤ）法又は化学蒸着（ＣＶＤ）法によつて、凹所
１４内に銅合金を堆積させることである。この堆積は 1
50〔℃〕以下の堆積温度により行われるので、この段階
では合金元素の酸化物は形成されない。次に図３に示す
ように、 250〔℃〕ないし 400〔℃〕の温度で使用温度
の程度によつて決まる30分間ないし１時間の間構造３８
をアニール処理して、酸素含有絶縁体層１６に接触して
いる銅合金プラグ４２の表面及び露出しているプラグ４
２の表面だけに、合金元素の酸化物の薄膜層４０を形成
させる。絶縁層１６が二酸化ケイ素である場合、この薄
膜層４０は合金元素の酸化物となる。絶縁層１６がポリ
イミドである場合、合金元素はポリイミド内の酸素と同
様に炭素とも反応するので薄膜層４０は合金元素の酸化
物−炭化物層となる。 250〔℃〕ないし 400〔℃〕の温
度において合金元素が、図３の矢印で示すように酸素と
接触している銅合金プラグ４２の面に凝離し、酸素と反
応して酸化物層４０を形成する。合金元素が絶縁層１６
内の酸素と反応している間に、酸化物層４０の小部分が
絶縁層１６内に侵入する。図３の破線は、合金元素が絶
縁層１６と反応して薄膜酸化物層４０を形成する前の絶
縁層１６の本来の境界を示す。酸化物層４０の厚さは50
〔Å〕ないし100〔Å〕である。合金元素酸化物の生成
エネルギーは酸化銅の生成エネルギーよりも高いので、
合金元素酸化物が最初に生成され、銅が酸化物層４０に
侵入することを阻止する。従つて酸化銅は形成されな
い。In FIG. 2, the second step in one embodiment of the present invention is to deposit a copper alloy in the recess 14 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) such as vapor deposition or sputtering. That is. This deposit is 1
Since the deposition is performed at a deposition temperature of 50 ° C. or less, no oxide of alloying elements is formed at this stage. Next, as shown in FIG. 3, the structure 38 is used at a temperature of 250 [° C.] to 400 [° C.] for 30 minutes to 1 hour depending on the degree of operating temperature.
Is annealed to expose the surface of the copper alloy plug 42 in contact with the oxygen-containing insulator layer 16 and the exposed plug 4
The thin film layer 40 of the oxide of the alloying element is formed only on the surface of 2. When the insulating layer 16 is silicon dioxide, the thin film layer 40 is an oxide of an alloy element. When the insulating layer 16 is polyimide, the alloy element reacts with carbon as well as oxygen in the polyimide, so that the thin film layer 40 becomes an oxide-carbide layer of the alloy element. At a temperature of 250 [° C.] to 400 [° C.], alloying elements segregate on the surface of the copper alloy plug 42 in contact with oxygen as shown by the arrow in FIG. 3 and react with oxygen to form the oxide layer 40. Form. The alloy element is the insulating layer 16
A small portion of oxide layer 40 penetrates into insulating layer 16 while reacting with oxygen therein. The broken line in FIG. 3 indicates the original boundary of the insulating layer 16 before the alloy element reacts with the insulating layer 16 to form the thin film oxide layer 40. The thickness of the oxide layer 40 is 50
It is [Å] or 100 [Å]. Since the formation energy of alloying element oxide is higher than that of copper oxide,
The alloying element oxide is first formed and prevents copper from entering the oxide layer 40. Therefore, no copper oxide is formed.
【００１８】最終的な結果として、図１に示すように銅
合金プラグ３０及び酸化物層３２からなるバイア、ライ
ン又は他の凹所１４を有する相互接続構造２８を得る。
合金元素の凝離に起因して、銅合金プラグ３０は凝離以
前の銅合金内に元々含まれていた量の約半分の合金元素
を含む。例えば、銅合金が原子百分率 2.0〔％〕の合金
元素を含んでいるならば、銅合金プラグ３０は原子百分
率 1.0〔％〕の銅合金を含むことになる。さらに、酸化
物層３２は累進的な層であり、酸化物層３２内の酸化物
濃度は面１５、１７及び１９からそれぞれ面２１、２３
及び２５に向けて漸増している。また本発明は相互接続
構造２８を提供する。The net result is an interconnect structure 28 having vias, lines or other recesses 14 of copper alloy plugs 30 and oxide layers 32 as shown in FIG.
Due to the segregation of the alloying elements, the copper alloy plug 30 contains about half the alloying elements originally contained in the copper alloy prior to segregation. For example, if the copper alloy contains an atomic percentage of 2.0% alloy elements, the copper alloy plug 30 will contain an atomic percentage of 1.0% copper alloy. Further, the oxide layer 32 is a progressive layer, and the oxide concentration in the oxide layer 32 varies from faces 15, 17 and 19 to faces 21, 23, respectively.
And 25. The present invention also provides an interconnect structure 28.
【００１９】絶縁層１６上にさらに他の絶縁層を堆積さ
せ、絶縁層内に凹所を設けることによつてこれらの層内
に相互接続を生成させるようにしても良いことを当該分
野の知識を有する者は理解するであろう。絶縁層１６上
に堆積される絶縁層がポリイミドの場合、それは、 350
〔℃〕ないし 400〔℃〕で30分間ないし１時間の養生処
理をする必要がある。この養生処理の間に、酸化物層４
０が生成される。かくして当該アニールステツプは独立
のステツプである必要はなく、その後の相互接続形成に
用いられる処理に組み込まれても良い。It is understood in the art that additional insulating layers may be deposited on the insulating layer 16 and recesses may be made in the insulating layers to create interconnects in these layers. Those who have will understand. If the insulating layer deposited on insulating layer 16 is polyimide, it is
It is necessary to carry out curing treatment at [° C] to 400 [° C] for 30 minutes to 1 hour. During this curing process, the oxide layer 4
0 is generated. Thus, the anneal step need not be a separate step, but may be incorporated into the process used to form subsequent interconnects.
【００２０】本発明の精神及び範囲から脱することな
く、上述のステツプの順序を変更することができること
を当該分野の知識を有する者は理解できる。例えば、上
述したようにＣＶＤ又はＰＶＤによつて、銅導電性ライ
ン１８上に最初に銅合金が堆積させられても良い。次
に、当該堆積された合金は周知のリソグラフイ技術及び
エツチング技術によつてパターン化され得る。最後のス
テツプは絶縁層１６を堆積させることである。絶縁層１
６がポリイミドである場合、上述のようにポリイミドに
養生処理を施さなければならない。絶縁層１６が二酸化
ケイ素である場合、それはＣＶＤ法によつて堆積させら
れてもＰＶＤ法によつて堆積させられても良い。Those skilled in the art will appreciate that the order of the steps described above may be changed without departing from the spirit and scope of the invention. For example, a copper alloy may first be deposited on the copper conductive lines 18 by CVD or PVD as described above. The deposited alloy can then be patterned by well-known lithographic and etching techniques. The final step is to deposit the insulating layer 16. Insulation layer 1
If 6 is a polyimide, the polyimide must be aged as described above. If insulating layer 16 is silicon dioxide, it may be deposited by a CVD method or a PVD method.
【００２１】本発明の他の実施例において、第２のすな
わち最終ステツプは、銅合金プラグ４２及び薄膜酸化物
層４０を単一ステツプにより形成する。プラグ４２及び
酸化物層４０は、合金元素の酸化物の薄膜層４０を生じ
させる堆積温度で凹所１４内に本発明の銅合金を堆積さ
せることにより形成される。この実施例においては、堆
積温度が 150〔℃〕ないし 250〔℃〕の範囲内にあれ
ば、銅合金をＣＶＤ法によつて堆積させることもでき、
ＰＶＤ法によつて堆積させることもできる。この実施例
における酸化物層及び銅合金プラグの形成は図３に示す
ように上述したことと同様である。既に述べたように合
金元素が銅合金の、酸素と接触している面に凝離し、酸
素と反応して酸化物層４０を形成する。合金元素及び絶
縁層１６内の酸素間の反応に起因して、酸化物層４０の
小部分は絶縁層１６内に侵入する。合金元素酸化物の生
成エネルギーは酸化銅の生成エネルギーよりも高いの
で、酸化銅は生じない。In another embodiment of the invention, the second or final step forms the copper alloy plug 42 and the thin oxide layer 40 in a single step. The plug 42 and oxide layer 40 are formed by depositing the copper alloy of the present invention in the recess 14 at a deposition temperature that results in a thin film layer 40 of oxide of the alloying element. In this embodiment, if the deposition temperature is in the range of 150 [° C.] to 250 [° C.], the copper alloy can be deposited by the CVD method,
It can also be deposited by the PVD method. The formation of the oxide layer and the copper alloy plug in this embodiment is the same as described above as shown in FIG. As described above, the alloying element segregates on the surface of the copper alloy that is in contact with oxygen and reacts with oxygen to form the oxide layer 40. Due to the reaction between the alloying elements and oxygen in the insulating layer 16, a small portion of the oxide layer 40 penetrates into the insulating layer 16. Since the formation energy of the alloying element oxide is higher than the formation energy of copper oxide, copper oxide does not occur.
【００２２】絶縁体が二酸化ケイ素であり、合金元素と
してアルミニウム又はクロムが使用される場合の薄膜層
３２はそれぞれ、酸化アルミニウム（Ａｌ2Ｏ3 ）又は
酸化クロム（Ｃｒ2 Ｏ3 ）からなる。酸化物層３２は好
ましい機能を実現する。純粋な銅は絶縁体に良好には接
着しない。しかしながら純粋なアルミニウム及び純粋な
クロムは、純粋な銅より格段的に良好に酸素含有絶縁体
に接着する。さらに、酸化アルミニウム及び酸化クロム
は極めて優れた銅との接着性を有している。従つて酸化
物層３２は接着剤として作用し、銅合金を酸素含有絶縁
体層１６に接着させることができる。２番目の機能とし
て酸化物層３２は表面保護層として作用し、これにより
堆積した銅合金の耐食性を改善する。最後の機能として
酸化物層３２は、例えば丘状の物理的な歪みを生じさせ
ない点において改善をする。When the insulator is silicon dioxide and aluminum or chromium is used as the alloying element, the thin film layers 32 are made of aluminum oxide (Al 2 O 3 ) or chromium oxide (Cr 2 O 3 ), respectively. The oxide layer 32 achieves the desired function. Pure copper does not adhere well to insulators. However, pure aluminum and pure chromium adhere to oxygen-containing insulators significantly better than pure copper. Further, aluminum oxide and chromium oxide have extremely excellent adhesion to copper. Accordingly, the oxide layer 32 acts as an adhesive, allowing the copper alloy to adhere to the oxygen-containing insulator layer 16. As a second function, the oxide layer 32 acts as a surface protective layer, thereby improving the corrosion resistance of the deposited copper alloy. As a final function, the oxide layer 32 improves on the fact that it does not cause, for example, hill-like physical strain.
【００２３】本発明は、従来技術の接着層を使用するＢ
ＥＯＬ銅金属処理を大幅に改善する。まず第１に、本発
明の方法はただ１つの堆積ステツプを使用するが、従来
の技術は２つの堆積ステツプを必要とし、そのうちの１
つは接着層を堆積させるステツプであり第２のステツプ
は銅プラグを堆積させるステツプである。第２に、酸化
物層３２は絶縁層１６の内側に偏つて生じ、しかも50
〔Å〕ないし 100〔Å〕の厚さに過ぎないので、銅合金
プラグ３０の利用し得る断面積を増大させ、これによつ
てミクロン以下のラインの電流導通能力を増大させる。
さらに、銅合金プラグ３０のコンダクタンスは純粋な銅
のコンダクタンスより小さいが、原子百分率 1.0〔％〕
以下に合金元素を抑えることにより、合金に起因するコ
ンダクタンスの低下を銅合金プラグ３０の断面積を増大
させることによつて相殺する。酸素と接触している銅合
金の面だけに酸化物層が生成するので、銅合金プラグ３
０は銅導電ライン１８に直接接触する。かくして本発明
の金属処理は、接着層を使用する従来技術の金属処理に
存在する直列抵抗及び接触抵抗を除去できる。The present invention uses a prior art adhesive layer B
Significantly improves EOL copper metal processing. First of all, while the method of the present invention uses only one deposition step, the prior art requires two deposition steps, one of which is
One is the step of depositing the adhesion layer and the second step is the step of depositing the copper plug. Second, the oxide layer 32 is unevenly generated inside the insulating layer 16, and
Since it is only [Å] to 100 [Å] thick, it increases the available cross-sectional area of the copper alloy plug 30, thereby increasing the current carrying capability of submicron lines.
Furthermore, the conductance of the copper alloy plug 30 is smaller than that of pure copper, but the atomic percentage is 1.0 [%].
By suppressing the alloy elements below, the decrease in conductance due to the alloy is offset by increasing the cross-sectional area of the copper alloy plug 30. Since the oxide layer is formed only on the surface of the copper alloy which is in contact with oxygen, the copper alloy plug 3
0 directly contacts the copper conductive line 18. Thus, the metallization of the present invention can eliminate the series resistance and contact resistance present in prior art metallizations that use adhesive layers.
【００２４】図４は、本発明の方法に従つて形成された
銅合金プラグ４６及び酸化物層４８を有する他のＶＬＳ
Ｉ相互接続構造４４の一部にあるライン又は凹所を示す
断面図である。構造４４はシリコン基板２６を含み、シ
リコン基板２６内にはケイ化金属コンタクト２４が形成
される。例えばケイ化金属コンタクト２４は金属酸化膜
半導体（ＭＯＳ）型のＶＬＳＩ素子のソース領域、ドレ
イン領域又はゲート領域に形成されたケイ化金属コンタ
クトとして使用し得る。コンタクト２４はケイ化タンタ
ル（ＴａＳｉ2 ）又はケイ化コバルト（ＣｏＳｉ2 ）に
よつて構成するようにしても良い。バイア１４はコンタ
クト２４への導電性接続を果たすための手段である。さ
らに構造４４は凹所１４の底部に形成された拡散障壁層
５０を含むことにより、銅合金プラグ４６内の銅が基板
２６内に拡散するのを防ぐ。ケイ化物コンタクト２４内
には酸素原子が存在しないので凹所１４の底部に酸化物
層は生成せず、このため拡散障壁層５０が必要となる。FIG. 4 illustrates another VLS having a copper alloy plug 46 and an oxide layer 48 formed according to the method of the present invention.
4 is a cross-sectional view showing a line or recess in a portion of I-interconnection structure 44. FIG. Structure 44 includes a silicon substrate 26 in which metal silicide contact 24 is formed. For example, the metal silicide contact 24 can be used as a metal silicide contact formed in the source region, drain region or gate region of a metal oxide semiconductor (MOS) type VLSI device. The contact 24 may be made of tantalum silicide (TaSi 2 ) or cobalt silicide (CoSi 2 ). Via 14 is a means for making a conductive connection to contact 24. Further, the structure 44 includes a diffusion barrier layer 50 formed at the bottom of the recess 14 to prevent the copper in the copper alloy plug 46 from diffusing into the substrate 26. Since there are no oxygen atoms in the silicide contact 24, no oxide layer forms at the bottom of the recess 14, which requires the diffusion barrier layer 50.
【００２５】図１、図２及び図３を参照して上述した本
発明の方法の実施例を、銅合金プラグ４６及び酸化物層
４８の形成に関して図４にも同じように適用することが
できる。図４の酸化物層４８は、図３の酸化物層３２と
同一の好ましい機能を実現する。本発明は本発明の方法
を使用することにより得られる相互接続構造４４を提供
する。The embodiment of the method of the present invention described above with reference to FIGS. 1, 2 and 3 can be similarly applied to FIG. 4 with respect to the formation of the copper alloy plug 46 and the oxide layer 48. .. The oxide layer 48 of FIG. 4 performs the same desired function as the oxide layer 32 of FIG. The present invention provides an interconnect structure 44 obtained by using the method of the present invention.
【００２６】図４の構造４４内に本発明を使用すること
は、従来技術の拡散障壁接着層を使用するＢＥＯＬ銅金
属処理を大幅に改善する。従来技術の相互接続構造２２
は、図６に示すようなＵ形の拡散障壁接着層２０を必要
とする。しかしながら本発明は、図４に示すように拡散
障壁５０及び酸化物層４８だけを必要とする。酸化物層
４８は絶縁層１６内に偏つて生成し、しかもその厚さは
50〔Å〕ないし 100〔Å〕に過ぎないので、利用できる
銅合金プラグ４６の断面積が増大し、これによりミクロ
ン以下のラインの電流導通能力が増大する。The use of the present invention in structure 44 of FIG. 4 greatly improves BEOL copper metal processing using prior art diffusion barrier adhesion layers. Prior art interconnection structure 22
Requires a U-shaped diffusion barrier adhesive layer 20 as shown in FIG. However, the present invention requires only diffusion barrier 50 and oxide layer 48 as shown in FIG. The oxide layer 48 is unevenly formed in the insulating layer 16, and its thickness is
Since it is only 50 [Å] to 100 [Å], the cross-sectional area of the available copper alloy plug 46 is increased, which increases the current carrying capability of the submicron lines.
【００２７】上述の通り本発明をその最適な実施例に基
づいて特定的に図示、説明したが、本発明の精神及び範
囲から脱することなく形式及び詳細構成の双方について
種々の変更を加えても良い。While the present invention has been particularly shown and described based on the preferred embodiments thereof as set forth above, various changes, both in form and detail, may be made without departing from the spirit and scope of the invention. Is also good.
【００２８】[0028]
【発明の効果】上述のように本発明によれば、拡散障壁
及び酸化物層だけを設けることにより、利用できる銅合
金プラグの断面積を増大させ、これによりラインの電流
導通能力を一段と増大させることができる。As described above, according to the present invention, by providing only the diffusion barrier and the oxide layer, the cross-sectional area of the available copper alloy plug is increased, thereby further increasing the current conducting ability of the line. be able to.
【図１】図１は本発明の方法により銅合金を堆積させる
ことにより薄膜酸化物層を形成した後のＶＬＳＩ相互接
続構造の一部にあるライン又は凹所を示す断面図であ
る。FIG. 1 is a cross-sectional view showing lines or recesses in a portion of a VLSI interconnect structure after forming a thin oxide layer by depositing a copper alloy by the method of the present invention.
【図２】図２は本発明の方法により銅合金を堆積させた
後のＶＬＳＩ相互接続構造の一部にあるライン又は凹所
を示す断面図である。FIG. 2 is a cross-sectional view showing lines or recesses in a portion of a VLSI interconnect structure after depositing a copper alloy by the method of the present invention.
【図３】図３は本発明の方法により薄膜酸化物層を形成
中のＶＬＳＩ相互接続構造の一部にあるライン又は凹所
を示す断面図である。FIG. 3 is a cross-sectional view showing a line or recess in a portion of a VLSI interconnect structure during the formation of a thin film oxide layer by the method of the present invention.
【図４】図４は本発明の方法により銅合金を堆積させる
ことにより薄膜酸化物層を形成した後の、他のＶＬＳＩ
相互接続構造の一部にあるライン又は凹所を示す断面図
である。FIG. 4 is another VLSI after forming a thin oxide layer by depositing a copper alloy by the method of the present invention.
FIG. 6 is a cross-sectional view showing a line or recess in a portion of an interconnect structure.
【図５】図５は従来技術の接着層を使用するＶＬＳＩ相
互接続構造の一部にあるライン又は凹所を示す断面図で
ある。FIG. 5 is a cross-sectional view showing lines or recesses in a portion of a VLSI interconnect structure using a prior art adhesive layer.
【図６】図６は従来技術による拡散障壁接着層を使用す
る他のＶＬＳＩ相互接続構造の一部にあるライン又は凹
所を示す断面図である。FIG. 6 is a cross-sectional view showing lines or recesses in a portion of another VLSI interconnect structure using a diffusion barrier adhesion layer according to the prior art.
１０、２２、２８、３８、４４……ＶＬＳＩ相互接続構
造、１２、３０、４２、４６……銅合金プラグ、１４…
…バイアすなわち凹所、１５、１７、１９、２１、２
３、２５……酸化物層の面、１６……酸素含有絶縁層、
１８……銅の導電ライン、２０……接着層、２４……ケ
イ化金属コンタクト、２６……シリコン基板、３２、４
０、４８……合金元素の酸化物層、３６……銅合金、５
０……拡散障壁層。10, 22, 28, 38, 44 ... VLSI interconnection structure, 12, 30, 42, 46 ... Copper alloy plug, 14 ...
… Vias or recesses, 15, 17, 19, 21, 2
3, 25 ... Oxide layer surface, 16 ... Oxygen-containing insulating layer,
18 ... Copper conductive line, 20 ... Adhesive layer, 24 ... Metal silicide contact, 26 ... Silicon substrate, 32, 4
0, 48 ... Oxide layer of alloy element, 36 ... Copper alloy, 5
0 ... Diffusion barrier layer.
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年６月２４日[Submission date] June 24, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２４[Correction target item name] 0024
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２４】図４は、本発明の方法に従つて形成された
銅合金プラグ４６及び酸化物層４８を有する他のＶＬＳ
Ｉ相互接続構造４４の一部にあるライン又は凹所を示す
断面図である。構造４４はシリコン基板２６を含み、シ
リコン基板２６内にはケイ化金属コンタクト２４が形成
される。例えばケイ化金属コンタクト２４は金属酸化膜
半導体（ＭＯＳ）型のＶＬＳＩ素子のソース領域、ドレ
イン領域又はゲート領域に形成されたケイ化金属コンタ
クトとして使用し得る。コンタクト２４はケイ化タンタ
ル（ＴａＳｉ２）又はケイ化コバルト（ＣｏＳｉ２）に
よつて構成するようにしても良い。バイア１４はコンタ
クト２４への導電性接続を果たすための手段である。さ
らに構造４４は凹所１４の底部に形成された拡散障壁層
５０（耐火性金属からなる）を含むことにより、銅合金
プラグ４６内の銅が基板２６内に拡散するのを防ぐ。ケ
イ化物コンタクト２４内には酸素原子が存在しないので
凹所１４の底部に酸化物層は生成せず、このため拡散障
壁層５０が必要となる。FIG. 4 illustrates another VLS having a copper alloy plug 46 and an oxide layer 48 formed according to the method of the present invention.
4 is a cross-sectional view showing a line or recess in a portion of I-interconnection structure 44. FIG. Structure 44 includes a silicon substrate 26 in which metal silicide contact 24 is formed. For example, the metal silicide contact 24 can be used as a metal silicide contact formed in the source region, drain region or gate region of a metal oxide semiconductor (MOS) type VLSI device. The contact 24 may be made of tantalum silicide (TaSi 2 ) or cobalt silicide (CoSi 2 ). Via 14 is a means for making a conductive connection to contact 24. Further, the structure 44 includes a diffusion barrier layer 50 (comprising a refractory metal) formed at the bottom of the recess 14 to prevent the copper in the copper alloy plug 46 from diffusing into the substrate 26. Since there are no oxygen atoms in the silicide contact 24, no oxide layer forms at the bottom of the recess 14, which requires the diffusion barrier layer 50.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【特許請求の範囲】[Claims]
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ジエームス・マツケル・エドウイン・ハー パー アメリカ合衆国、ニユーヨーク州10598、 ヨークタウン・ヘイツト、エリザベス・ロ ード 507番地 (72)発明者 カレン・リン・ホロウエイ アメリカ合衆国、ニユーヨーク州10549、 マウント・キスコ、アパートメント２、ウ エスト・ストリート ２番地 (72)発明者 トーマス・ユ−キウ・クオツク アメリカ合衆国、ニユージヤージー州 07675、ウエストウツド、ビーチ・ストリ ート 735番地 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor James Mazkel Edwin Harper United States, New York, USA 10598, Yorktown Hatet, Elizabeth Road 507 (72) Inventor Karen Lin Hollowey United States, New York State 10549, Mount Kisco, Apartment 2, West Street No. 2 (72) Inventor Thomas Yuuki Quotsk New York 07675, United States 07675, West Woods, Beach Street 735
Claims (6)
素含有絶縁体層内に形成されたＶＬＳＩ相互接続構造の
凹所内に銅合金導電プラグを形成する方法において、 銅及び原子百分率 2.0〔％〕未満の合金元素からなる銅
合金を形成するステツプと、 上記相互接続構造の凹所内に上記銅合金を堆積させると
共に、銅合金プラグ並びに上記プラグの露出している表
面及び上記プラグの上記酸素含有絶縁体に接触している
面に上記合金元素の酸化物の薄膜層を形成するステツプ
とを含むことを特徴とする銅合金導電プラグ形成方法。1. A method of forming a copper alloy conductive plug in a recess of a VLSI interconnect structure formed in an oxygen-containing insulator layer located on one major plane of a substrate, comprising copper and atomic percentage 2.0. A step of forming a copper alloy comprising less than [%] of alloying elements, depositing the copper alloy in the recess of the interconnect structure, and exposing the copper alloy plug and the exposed surface of the plug and the plug And a step of forming a thin film layer of the oxide of the alloying element on the surface in contact with the oxygen-containing insulator.
同時に上記薄膜酸化物層を形成することができる堆積温
度により上記銅合金を堆積させる処理を含むことを特徴
とする請求項１に記載の銅合金導電プラグ形成方法。2. The deposition step comprises the step of depositing the copper alloy at a deposition temperature capable of forming the thin film oxide layer simultaneously with the deposition of the copper alloy. Method for forming copper alloy conductive plug of.
理と、 上記相互接続構造をアニール処理することにより上記薄
膜酸化物層を形成させる処理とを含むことを特徴とする
請求項１に記載の銅合金導電プラグ形成方法。3. The deposition step includes the steps of depositing the copper alloy in the recesses of the interconnect structure and annealing the interconnect structure to form the thin film oxide layer. The method for forming a copper alloy conductive plug according to claim 1, wherein
され、上記基板の上部面の一部及び上記プラグの底部面
に接触している耐火性金属障壁層と、 上記基板の上部内に形成され、上記障壁層の底部面に接
触しているケイ化金属層とを含むことを特徴とする請求
項１に記載の銅合金導電プラグ形成方法。4. A refractory metal barrier layer formed on the bottom of the recess and in contact with a portion of the top surface of the substrate and the bottom surface of the plug, and a substrate within the top of the substrate. And a metal silicide layer in contact with the bottom surface of the barrier layer, the method of claim 1, further comprising:
も１つの酸素含有絶縁体層を有する基板と、 上記酸素含有絶縁体に設けられた凹所内に形成された導
電性プラグを含み、上記導電性プラグは、銅及び原子百
分率 2.0〔％〕未満の合金元素からなる銅合金並びに上
記銅合金の露出している表面及び上記銅合金の上記酸素
含有絶縁体に接触している面に形成された上記合金元素
の酸化物層とを含むことを特徴とするＶＬＳＩ相互接続
構造。5. A substrate having at least one oxygen-containing insulator layer formed on one major plane, and a conductive plug formed in a recess provided in the oxygen-containing insulator. The conductive plug is formed on a copper alloy composed of copper and an alloy element having an atomic percentage of less than 2.0 (%), an exposed surface of the copper alloy, and a surface of the copper alloy in contact with the oxygen-containing insulator. And a VLSI interconnect structure comprising an oxide layer of the above alloy element.
記基板の上部面の一部に接触している耐火性金属障壁層
と、 上記基板の上部内に形成され、上記障壁層の底部面に接
触しているケイ化金属層とを含むことを特徴とする請求
項５に記載のＶＬＳＩ相互接続構造。6. The refractory metal barrier layer formed on the bottom of the recess and in contact with the bottom surface of the plug and a part of the top surface of the substrate, and a substrate inside the top of the substrate. 6. A VLSI interconnect structure according to claim 5, further comprising a metal silicide layer formed in contact with a bottom surface of the barrier layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/681,798 US5130274A (en) | 1991-04-05 | 1991-04-05 | Copper alloy metallurgies for VLSI interconnection structures |
| US07/681798 | 1991-04-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102318A true JPH05102318A (en) | 1993-04-23 |
| JPH0760852B2 JPH0760852B2 (en) | 1995-06-28 |
Family
ID=24736866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4081500A Expired - Fee Related JPH0760852B2 (en) | 1991-04-05 | 1992-03-03 | Method and apparatus for forming copper alloy conductive plug |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5130274A (en) |
| EP (1) | EP0508156A1 (en) |
| JP (1) | JPH0760852B2 (en) |
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| JPS61243447A (en) * | 1985-04-22 | 1986-10-29 | Asahi Chem Ind Co Ltd | Formation of pattern |
| JPS6464338A (en) * | 1987-09-04 | 1989-03-10 | Hitachi Ltd | Wiring for semiconductor device |
| JPS6477143A (en) * | 1987-09-18 | 1989-03-23 | Toshiba Corp | Formation of copper thin film wiring |
| JPH02114639A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | Semiconductor device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3631304A (en) * | 1970-05-26 | 1971-12-28 | Cogar Corp | Semiconductor device, electrical conductor and fabrication methods therefor |
| JPS5533004A (en) * | 1978-08-29 | 1980-03-08 | Tamagawa Kikai Kinzoku Kk | Lead material for semiconductor |
| JPS55107257A (en) * | 1979-01-08 | 1980-08-16 | Toshiba Corp | Ohmic electrode |
| US4434434A (en) * | 1981-03-30 | 1984-02-28 | International Business Machines Corporation | Solder mound formation on substrates |
| US4816425A (en) * | 1981-11-19 | 1989-03-28 | Texas Instruments Incorporated | Polycide process for integrated circuits |
| JPS607162A (en) * | 1983-06-24 | 1985-01-14 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
| US4566177A (en) * | 1984-05-11 | 1986-01-28 | Signetics Corporation | Formation of electromigration resistant aluminum alloy conductors |
| JPS62113421A (en) * | 1985-11-13 | 1987-05-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62214632A (en) * | 1986-03-14 | 1987-09-21 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| EP0261846B1 (en) * | 1986-09-17 | 1992-12-02 | Fujitsu Limited | Method of forming a metallization film containing copper on the surface of a semiconductor device |
| US4784973A (en) * | 1987-08-24 | 1988-11-15 | Inmos Corporation | Semiconductor contact silicide/nitride process with control for silicide thickness |
| JP2511289B2 (en) * | 1988-03-30 | 1996-06-26 | 株式会社日立製作所 | Semiconductor device |
| JPH0250432A (en) * | 1988-08-12 | 1990-02-20 | Toshiba Corp | Semiconductor device |
| JP2839579B2 (en) * | 1989-10-02 | 1998-12-16 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-04-05 US US07/681,798 patent/US5130274A/en not_active Expired - Lifetime
-
1992
- 1992-03-03 JP JP4081500A patent/JPH0760852B2/en not_active Expired - Fee Related
- 1992-03-14 EP EP92104442A patent/EP0508156A1/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61243447A (en) * | 1985-04-22 | 1986-10-29 | Asahi Chem Ind Co Ltd | Formation of pattern |
| JPS6464338A (en) * | 1987-09-04 | 1989-03-10 | Hitachi Ltd | Wiring for semiconductor device |
| JPS6477143A (en) * | 1987-09-18 | 1989-03-23 | Toshiba Corp | Formation of copper thin film wiring |
| JPH02114639A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | Semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6656828B1 (en) | 1999-01-22 | 2003-12-02 | Hitachi, Ltd. | Method of forming bump electrodes |
| US7943517B2 (en) | 2004-02-27 | 2011-05-17 | Semiconductor Technology Academic Research Center | Semiconductor device with a barrier film |
| US8133813B2 (en) | 2004-02-27 | 2012-03-13 | Semiconductor Technology Academic Research Center | Semiconductor device with a barrier film |
| JP2006073863A (en) * | 2004-09-03 | 2006-03-16 | Nikko Materials Co Ltd | Copper alloy wiring for semiconductor, sputtering target and forming method of copper alloy wiring for semiconductor |
| US7935624B2 (en) | 2006-01-20 | 2011-05-03 | Fujitsu Semiconductor Limited | Fabrication method of semiconductor device having a barrier layer containing Mn |
| WO2008149751A1 (en) * | 2007-05-30 | 2008-12-11 | Tokyo Electron Limited | Process for producing semiconductor device, semiconductor production apparatus, and recording medium |
| JP2012156545A (en) * | 2012-04-12 | 2012-08-16 | Jx Nippon Mining & Metals Corp | Copper alloy wire for semiconductor and sputtering target, and method for forming copper alloy wire for semiconductor |
| JP2014112692A (en) * | 2013-12-27 | 2014-06-19 | Jx Nippon Mining & Metals Corp | Copper alloy wiring for semiconductor and sputtering target and method of forming copper alloy wiring for semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0760852B2 (en) | 1995-06-28 |
| EP0508156A1 (en) | 1992-10-14 |
| US5130274A (en) | 1992-07-14 |
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