JPH05102225A - 半導体製造装置 - Google Patents

半導体製造装置

Info

Publication number
JPH05102225A
JPH05102225A JP25932691A JP25932691A JPH05102225A JP H05102225 A JPH05102225 A JP H05102225A JP 25932691 A JP25932691 A JP 25932691A JP 25932691 A JP25932691 A JP 25932691A JP H05102225 A JPH05102225 A JP H05102225A
Authority
JP
Japan
Prior art keywords
wire
external connection
semiconductor integrated
integrated circuit
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25932691A
Other languages
English (en)
Inventor
Jun Taniguchi
潤 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25932691A priority Critical patent/JPH05102225A/ja
Publication of JPH05102225A publication Critical patent/JPH05102225A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】半導体集積回路の多機能化、高機能化に伴なう
電極パッド数、外部接続端子数の増加と共にワイヤ長さ
も長くなることにより、ワイヤボンディング時の隣接ワ
イヤとの接触やワイヤたれを防止する。 【構成】半導体集積回路と外部接続端子との間でワイヤ
直下となる位置に各電極パッドと外部接続端子を接続し
ているワイヤの間隔と同一の間隔で溝を設ける。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体集積回路表面に
形成された電極パッドとリードフレームのリードや、セ
ラミック基板あるいは樹脂基板表面に形成された配線パ
ターン（以下、リードフレームのリードやセラミック基
板あるいは樹脂基板表面に形成された配線パターンを単
に外部接続端子と呼ぶ）とをワイヤにて接続する半導体
製造装置に関するものである。
【０００２】
【従来の技術】半導体集積回路表面に形成された電極パ
ッドと外部接続端子２とをワイヤにて接続することをワ
イヤボンディングと言う。
【０００３】ここでは、ワイヤボンディングの方式のひ
とつであるボールボンディングの説明をする。まず先端
の尖った貫通孔を持った筒状のツール（以下キャピラリ
と呼ぶ）にワイヤを通して、そのワイヤ先端をキャピラ
リ下端よりわずかにと突出させ、その突出端を電気溶融
することにより球状にし、電極パッド上にキャピラリを
移動させ、加圧、超音波振動より接合する。次に、ワイ
ヤを送りながら外部接続端子上にキャピラリを移動させ
加圧、超音波振動により接合しながら、ワイヤを切断す
る。以上の動作を電極パッドと外部接続端子との接続本
数分繰り返される方法である。
【０００４】
【発明が解決しようとする課題】近年、半導体集積回路
は、多機能化、高機能化が著しく進み、それに伴ない電
極パッド数や外部接続端子数も増加の一途をたどる一方
である。それとあいまって半導体集積回路の小型化に伴
ない電極パッドピッチの微細化も進んでいるが、外部接
続端子側の微細化は遅れており、半導体集積回路から遠
い位置に、外部接続端子を配置しなくてはならず、半導
体集積回路表面の電極パッドと外部接続端子間を長いワ
イヤを用いて接続しなくてはならない。
【０００５】しかし、ワイヤボンディング装置繰り返し
再現性精度によるキャピピラリ軌跡コントロールばらつ
きの為ワイヤの曲がり、たれによる隣接ワイヤとの接触
や半導体集積回路との接触はワイヤが長くなる程発生し
やすくなる。
【０００６】そこで、本発明の目的は、上記のような問
題を解決しようとするものであり、ワイヤ曲がり、たれ
による隣接ワイヤとの接触や半導体集積回路との接触を
防止することにより、長いワイヤを用いた半導体装置の
製造品質安定化を実現させるものである。
【０００７】
【課題を解決するための手段】本発明の半導体製造装置
は、半導体集積回路と外部接続端子の間でワイヤ直下と
なる位置に、各電極パッドと外部接続端子を接続してい
るワイヤの間隔と同一の間隔に溝を有するブロックを設
けたことを特徴とする。
【０００８】
【作用】本発明の上記の構造により、電極パッドと外部
接続端子をワイヤで接続する際ワイヤはブロックの溝に
はまり込むことによりループ形状が矯正され、ワイヤ曲
がり、たれの発生を防止できる。
【０００９】
【実施例】図１は本発明の実施例を示しており、半導体
集積回路表面の電極パッドと外部接続端子を接合する
際、ブロックを設けることにより、ワイヤのループ形
状、隣接するワイヤとの間隔を矯正させることを模式的
に示した平面図、図２は側面図である。
【００１０】半導体集積回路と外部接続端子との間でワ
イヤ直下となる位置に半導体集積回路の各辺に設置し、
各電極パッドと外部接続端子を接続しているワイヤの間
隔と同一の間隔で溝を設けてある。溝の下面の曲線は、
理想的なループ形状を作りだす部分であり、ワイヤを電
極パッド接合後、キャピラリを移動させ外部接続端子へ
接合する際、溝にはまり込むことによりループ形状は矯
正され、ワイヤのたれは防止される。
【００１１】又、ブロックに溝を設けてあることによ
り、ワイヤボンディング最中の隣接するワイヤとの接触
を防止している。
【００１２】その他、溝の上部にテーパを設けることに
よりワイヤボンディング装置繰り返し再現性精度による
キャピラリ軌跡コントロールのばらつきの為に生ずる接
合位置のばらつきが発生した場合でも上記テーパになら
って溝にはまり込むようになっており、安定したループ
形状、隣接ワイヤとの間隔を保つことができるようにな
っている。
【００１３】一半導体装置ワイヤボンディング完了後ブ
ロックは下降し、次の半導体装置が供給された後再度上
昇するようになっている。
【００１４】
【発明の効果】以上述べたように本発明によれば、半導
体集積回路と外部接続端子との間でワイヤ直下となる位
置に各電極パッドと外部接続端子を接続しているワイヤ
の間隔と同一の間隔で溝を設けることにより、ワイヤボ
ンディング時の隣接ワイヤとの接触、ワイヤたれを防止
することにより、長いワイヤを用いた半導体装置の製造
品質安定化向上の効果がある。
【図面の簡単な説明】
【図１】本発明の実施例を模式的に示す平面図である。
【図２】本発明の実施例を模式的に示す側面図である。
【符号の説明】
１ ブロック ２ 外部接続端子 ３ 半導体集積回路 ４ 電極パッド ５ ワイヤ

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 半導体集積回路３の表面に形成された電
    極パッド４と、リードフレームのリードや、セラミック
    基板あるいは樹脂基板表面に形成された配線パターンと
    を導電性細線（以下ワイヤと呼ぶ）にて接続するワイヤ
    ボンディング装置において、半導体集積回路とリードの
    間でワイヤ直下となる位置に、各電極パッドとリードを
    接続しているワイヤ５の間隔と同一の間隔に溝を有する
    ブロック１を設けたことにより、ワイヤの曲がり、たれ
    を規制することを特徴とした半導体製造装置。
JP25932691A 1991-10-07 1991-10-07 半導体製造装置 Pending JPH05102225A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25932691A JPH05102225A (ja) 1991-10-07 1991-10-07 半導体製造装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25932691A JPH05102225A (ja) 1991-10-07 1991-10-07 半導体製造装置

Publications (1)

Publication Number Publication Date
JPH05102225A true JPH05102225A (ja) 1993-04-23

Family

ID=17332538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25932691A Pending JPH05102225A (ja) 1991-10-07 1991-10-07 半導体製造装置

Country Status (1)

Country Link
JP (1) JPH05102225A (ja)

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