JPH05102223A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPH05102223A
JPH05102223A JP3259324A JP25932491A JPH05102223A JP H05102223 A JPH05102223 A JP H05102223A JP 3259324 A JP3259324 A JP 3259324A JP 25932491 A JP25932491 A JP 25932491A JP H05102223 A JPH05102223 A JP H05102223A
Authority
JP
Japan
Prior art keywords
wire
capillary
wires
holes
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3259324A
Other languages
English (en)
Inventor
Jun Taniguchi
潤 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3259324A priority Critical patent/JPH05102223A/ja
Publication of JPH05102223A publication Critical patent/JPH05102223A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/8518—Translational movements
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【構成】ワイヤを供給する機構を複数有した半導体製造
装置を用い、キャピラリに設けた並列した複数個の貫通
孔のそれぞれにワイヤを通す。 【効果】ワイヤボンディング所要時間の短縮をすること
により半導体装置製造原価の低減、又、電極パッド上に
ワイヤを接合する際の位置精度安定性向上、ループ形状
安定性向上を実現する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体集積回路の表面
に形成された電極パッドと中継点とを導電性細線にて接
続するワイヤボンディング方法に関するものである。
【０００２】
【従来の技術】半導体集積回路表面に形成された電極パ
ッドとリードフレームのリードやセラミック基板あるい
は樹脂基板表面に形成された配線パターンとを導電性細
線３（以下ワイヤと呼ぶ）を用いて接続することをワイ
ヤボンディングと言う。
【０００３】ここでは、ワイヤボンディングの方法の一
つであるボールボンディングの説明をする。まず先端の
尖った貫通孔を持つ筒状のツール（以下キャピラリと呼
ぶ）にワイヤを通してそのワイヤ先端をキャピラリ下端
よりわずかに突出させ、その突出端を電気放電により加
熱溶融することにより球状にし、電極パッド上にキャピ
ラリを移動させ、加圧，超音波振動により接合する。次
に、ワイヤを送りながら外部接続端子上にキャピラリを
移動させ加圧，超音波振動により接合しながら、ワイヤ
を切断する。以上の動作を電極パッドと外部接続端子と
の接続本数分繰り返される方法である。
【０００４】
【発明が解決しようとする課題】近年、半導体集積回路
は、多機能化、高機能化が著しく進み、それに伴ない電
極パッド数や外部接続端子数も増加の一途をたどる一方
である。それとあいまって半導体集積回路の小型化に伴
ない電極パッドピッチの微細化も進んでいるが、外部接
続端子側の微細化は遅れており、半導体集積回路から遠
い位置に、外部接続端子を配置しなくてはならず、半導
体集積回路表面の電極パッドと外部接続端子間を長いワ
イヤを用いて接続しなくてはならない。
【０００５】しかし、ワイヤボンディング装置精度によ
るキャピラリ軌跡コントロールのばらつきや、ワイヤの
きず、ねじれ等により生ずる、ワイヤの曲がり、たるみ
はワイヤが長くなる程発生しやすくなる。
【０００６】そこで、ワイヤ長さをおさえる為、電極パ
ッドと外部接続端子との間に配線パターンを形成した基
板等の中継点を設けた半導体装置も発明されている。
【０００７】本発明の目的は、上記のような電極パッド
と外部接続端子との間に中継点を有する半導体装置のワ
イヤボンディング所要時間を短縮することにより半導体
装置製造原価の低減を実現することにある。
【０００８】
【課題を解決するための手段】本発明の半導体装置の製
造方法は、キャピラリ１に並列した複数個の貫通孔２を
設け、複数本のワイヤを通し、一度に複数本のワイヤボ
ンディングを行なうことを特徴とする。
【０００９】
【作用】本発明の上記の構造により、一度に複数本のワ
イヤボンディングを行なうことができ、ループ形状の安
定性、電極パッドのワイヤ接合位置の安定性を向上させ
ることができる。
【００１０】
【実施例】図１は本発明に用いるキャピラリの模式図で
あり、図１（ａ）は平面図、図１（ｂ）は側面図であ
る。本発明に用いるキャピラリの形状は、キャピラリ製
造用金型の新規製作を行ない、先端加圧接合部は従来の
キャピラリと同一、並列した貫通孔のピッチは電極パッ
ドのピッチと同一にすることにより得られる。
【００１１】図２から図５は、本発明の実施例を示す説
明図である。キャピラリの並列した複数個の貫通孔のそ
れぞれにワイヤを通し、そのワイヤ先端を電気放電によ
り球状にし、キャピラリを従来と同様の方法で移動さ
せ、電極パッド、中継点に加圧、超音波振動により接合
を行ない、ワイヤを切断する。
【００１２】この様に、ワイヤボンディング方法は、従
来と同様のままで、キャピラリの並列した貫通孔のピッ
チを電極パッドのピッチと同一にすることにより一度に
複数本のワイヤボンディングを行なうことができるよう
になる。
【００１３】又、キャピラリ貫通孔のピッチは固定とな
っている為、電極パッド上にワイヤを接合する際の位置
精度の安定性向上、その他、一度に複数本のワイヤボン
ディグを行なうことにより、ワイヤボンディング装置の
繰り返し再現性精度によるキャピラリ軌跡コントロール
のばらつきの為に発生するループ形状のばらつきの低減
させることができるという特徴をもっている。
【００１４】
【発明の効果】以上述べた様に本発明によれば、キャピ
ラリに並列した複数個の貫通孔を設けることにより、一
度に複数本のワイヤボンディングを行なうことができ
る。
【００１５】又、従来の一本ずつワイヤボンディングを
する方法では、ワイヤボンディング装置の繰り返し再現
性精度によるキャピラリ軌跡コントロール精度のばらつ
きによるループ形状のばらつきや電極パッド上にワイヤ
を接合する際のワイヤボンディング位置のばらつきが発
生することがあったが、一度に複数本ワイヤボンディン
グを行なうことにより上記不具合の発生頻度を低減する
ことができる。
【図面の簡単な説明】
【図１】本発明に用いるキャピラリの模式図であり、
（ａ）は平面図、（ｂ）は側面図である。
【図２】本発明の実施例のワイヤボンディングの順序を
示す側面図である。
【図３】本発明の実施例のワイヤボンディングの順序を
示す側面図である。
【図４】本発明の実施例のワイヤボンディングの順序を
示す側面図である。
【図５】本発明の実施例のワイヤボンディングの順序を
示す側面図である。
【図６】本発明に用いる半導体装置であり，（ａ）は平
面図、（ｂ）は側面図である。
【符号の説明】
１ キャピラリ ２ 貫通孔 ３ ワイヤ ４ 半導体集積回路 ５ 電極パッド ６ 中継点 ７ 外部接続端子

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 半導体集積回路４の表面に形成された電
    極パッド５と、リードフレーム等の外部接続端子７との
    間に、前記電極パッドのピッチと同一ピッチに配列され
    た導電性を有する中継点６（以下中継点と呼ぶ）が形成
    された半導体装置において、電極パッドと中継点とを貫
    通孔を持つボンディングツールに導電性細線を通し接続
    する際、前記ボンディングツールに並列した複数個の孔
    を設け、複数の導電性細線を通すことにより、一度に複
    数本のワイヤボンディングを行なうことを特徴とした半
    導体装置の製造方法。
JP3259324A 1991-10-07 1991-10-07 半導体装置の製造方法 Pending JPH05102223A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3259324A JPH05102223A (ja) 1991-10-07 1991-10-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3259324A JPH05102223A (ja) 1991-10-07 1991-10-07 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH05102223A true JPH05102223A (ja) 1993-04-23

Family

ID=17332509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3259324A Pending JPH05102223A (ja) 1991-10-07 1991-10-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPH05102223A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839640A (en) * 1996-10-23 1998-11-24 Texas Instruments Incorporated Multiple-tool wire bonder
KR100685869B1 (ko) * 2001-04-12 2007-02-23 앰코 테크놀로지 코리아 주식회사 범핑과 압착을 동시에 행하는 와이어본더
US8008183B2 (en) * 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839640A (en) * 1996-10-23 1998-11-24 Texas Instruments Incorporated Multiple-tool wire bonder
KR100685869B1 (ko) * 2001-04-12 2007-02-23 앰코 테크놀로지 코리아 주식회사 범핑과 압착을 동시에 행하는 와이어본더
US8008183B2 (en) * 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding

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