JPH048876B2 - - Google Patents
Info
- Publication number
- JPH048876B2 JPH048876B2 JP59189107A JP18910784A JPH048876B2 JP H048876 B2 JPH048876 B2 JP H048876B2 JP 59189107 A JP59189107 A JP 59189107A JP 18910784 A JP18910784 A JP 18910784A JP H048876 B2 JPH048876 B2 JP H048876B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- power supply
- level
- internal signal
- refresh
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59189107A JPS6166295A (ja) | 1984-09-10 | 1984-09-10 | 半導体メモリ |
US06/774,430 US4807197A (en) | 1984-09-10 | 1985-09-10 | Integrated circuit with function of monitoring an internal signal |
EP85111433A EP0174638B1 (en) | 1984-09-10 | 1985-09-10 | Integrated circuit with function of monitoring an internal signal |
DE8585111433T DE3585760D1 (de) | 1984-09-10 | 1985-09-10 | Integrierte schaltung mit einer ueberwachungsfunktion eines internen signales. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59189107A JPS6166295A (ja) | 1984-09-10 | 1984-09-10 | 半導体メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6166295A JPS6166295A (ja) | 1986-04-05 |
JPH048876B2 true JPH048876B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-02-18 |
Family
ID=16235481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59189107A Granted JPS6166295A (ja) | 1984-09-10 | 1984-09-10 | 半導体メモリ |
Country Status (4)
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4807196A (en) * | 1986-03-24 | 1989-02-21 | Nec Corporation | Refresh address counter test control circuit for dynamic random access memory system |
JP3225533B2 (ja) * | 1991-04-11 | 2001-11-05 | 日本電気株式会社 | ダイナミック型半導体メモリ装置 |
JPH04372790A (ja) * | 1991-06-21 | 1992-12-25 | Sharp Corp | 半導体記憶装置 |
KR100372245B1 (ko) * | 1995-08-24 | 2004-02-25 | 삼성전자주식회사 | 워드라인순차제어반도체메모리장치 |
WO1999019879A1 (en) * | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Dram core refresh with reduced spike current |
DE102006020098A1 (de) * | 2006-04-29 | 2007-10-31 | Infineon Technologies Ag | Speicherschaltung und Verfahren zum Auffrischen von dynamischen Speicherzellen |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4145760A (en) * | 1978-04-11 | 1979-03-20 | Ncr Corporation | Memory device having a reduced number of pins |
JPS55150192A (en) * | 1979-05-08 | 1980-11-21 | Nec Corp | Memory unit |
JPS5835783A (ja) * | 1981-08-24 | 1983-03-02 | Fujitsu Ltd | 半導体メモリ |
JPS5972153A (ja) * | 1982-10-18 | 1984-04-24 | Toshiba Corp | 半導体集積回路装置 |
JPS59104795A (ja) * | 1982-12-06 | 1984-06-16 | Mitsubishi Electric Corp | 半導体メモリ装置 |
-
1984
- 1984-09-10 JP JP59189107A patent/JPS6166295A/ja active Granted
-
1985
- 1985-09-10 DE DE8585111433T patent/DE3585760D1/de not_active Expired - Lifetime
- 1985-09-10 US US06/774,430 patent/US4807197A/en not_active Expired - Fee Related
- 1985-09-10 EP EP85111433A patent/EP0174638B1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4807197A (en) | 1989-02-21 |
JPS6166295A (ja) | 1986-04-05 |
EP0174638A3 (en) | 1989-09-13 |
DE3585760D1 (de) | 1992-05-07 |
EP0174638B1 (en) | 1992-04-01 |
EP0174638A2 (en) | 1986-03-19 |
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