JPH0467341B2 - - Google Patents

Info

Publication number
JPH0467341B2
JPH0467341B2 JP59094684A JP9468484A JPH0467341B2 JP H0467341 B2 JPH0467341 B2 JP H0467341B2 JP 59094684 A JP59094684 A JP 59094684A JP 9468484 A JP9468484 A JP 9468484A JP H0467341 B2 JPH0467341 B2 JP H0467341B2
Authority
JP
Japan
Prior art keywords
layer
base
pnp transistor
emitter
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59094684A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60240156A (ja
Inventor
Tatsu Toyabe
Takahiro Okabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59094684A priority Critical patent/JPS60240156A/ja
Publication of JPS60240156A publication Critical patent/JPS60240156A/ja
Publication of JPH0467341B2 publication Critical patent/JPH0467341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Bipolar Integrated Circuits (AREA)
JP59094684A 1984-05-14 1984-05-14 耐放射線半導体集積回路装置 Granted JPS60240156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59094684A JPS60240156A (ja) 1984-05-14 1984-05-14 耐放射線半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59094684A JPS60240156A (ja) 1984-05-14 1984-05-14 耐放射線半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS60240156A JPS60240156A (ja) 1985-11-29
JPH0467341B2 true JPH0467341B2 (enExample) 1992-10-28

Family

ID=14117030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59094684A Granted JPS60240156A (ja) 1984-05-14 1984-05-14 耐放射線半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS60240156A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009157488A1 (ja) 2008-06-24 2009-12-30 株式会社ニフコ クリップ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199775A (en) * 1974-09-03 1980-04-22 Bell Telephone Laboratories, Incorporated Integrated circuit and method for fabrication thereof
JPS5678154A (en) * 1979-11-29 1981-06-26 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009157488A1 (ja) 2008-06-24 2009-12-30 株式会社ニフコ クリップ

Also Published As

Publication number Publication date
JPS60240156A (ja) 1985-11-29

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term