JPH0461497B2 - - Google Patents
Info
- Publication number
- JPH0461497B2 JPH0461497B2 JP62114636A JP11463687A JPH0461497B2 JP H0461497 B2 JPH0461497 B2 JP H0461497B2 JP 62114636 A JP62114636 A JP 62114636A JP 11463687 A JP11463687 A JP 11463687A JP H0461497 B2 JPH0461497 B2 JP H0461497B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- concentration
- impurity region
- impurity
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置における拡散領域の不純
物濃度分布の形状とその形成法に関し、高耐圧化
構造、低抵抗の配線、加工性が容易、ならびに素
子特性が安定な半導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the shape of impurity concentration distribution in a diffusion region in a semiconductor device and its formation method, and relates to a structure with high breakdown voltage, wiring with low resistance, easy workability, The present invention also relates to a method of manufacturing a semiconductor device with stable device characteristics.
〔従来の技術〕
半導体装置の微細化にともない、拡散層深さを
浅く形成することが要求されており、そのために
拡散係数の小さい不純物が用いられる傾向にあ
る。その際、形成される接合の不純物濃度が急激
に変わるため接合耐圧が低下する。この現象は結
局素子の動作電源範囲の低下につながるばかり
か、素子の安定動作の寿命をも低下させてしま
う。[Prior Art] With the miniaturization of semiconductor devices, it is required to form a diffusion layer with a shallow depth, and there is a tendency for impurities with a small diffusion coefficient to be used for this purpose. At this time, since the impurity concentration of the formed junction changes rapidly, the junction breakdown voltage decreases. This phenomenon not only ultimately leads to a reduction in the operating power range of the device, but also shortens the stable operation life of the device.
また、チヤンネル長を短縮する例として、特開
昭51−19980号公報が挙げられる。 Further, as an example of shortening the channel length, Japanese Patent Application Laid-Open No. 1998-1980 can be cited.
従来の製造方法では、チヤンネル長を正確に制
御しながら、低濃度領域と高濃度領域を自己整合
的に設けることについては、配慮がされておら
ず、微細なMOSトランジスタを製造することは、
極めて困難であつた。
Conventional manufacturing methods do not take into consideration the self-alignment of low-concentration and high-concentration regions while accurately controlling the channel length, making it difficult to manufacture fine MOS transistors.
It was extremely difficult.
本発明は、ドレインの低濃度領域と高濃度領域
とが自己整合的に設けられた高密度で高耐圧化構
造の半導体装置の製造方法を提供することを目的
とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a high-density and high-voltage structure in which a low concentration region and a high concentration region of a drain are provided in a self-aligned manner.
〔問題点を解決するための手段〕
上記の目的は、2回にわたつて低濃度と高濃度
の不純物を導入してドレイン領域を形成する際、
ゲート電極を2回自己整合的に使用することによ
り達成される。[Means for solving the problem] The above purpose is to form a drain region by introducing impurities at a low concentration and a high concentration twice.
This is achieved by using the gate electrode twice in a self-aligned manner.
ドレインの低濃度領域と高濃度領域とがゲート
電極に対して自己整合的に形成されるため、両領
域の位置合わせ誤差が原理的にゼロとなり、高密
度、高耐圧化構造の半導体装置が提供できる。
Since the low-concentration region and the high-concentration region of the drain are formed in a self-aligned manner with respect to the gate electrode, the alignment error between the two regions is theoretically zero, providing a semiconductor device with a high-density, high-voltage structure. can.
以下、本発明を実施例を参照して詳細に説明す
る。実施例を述べる。
Hereinafter, the present invention will be explained in detail with reference to Examples. An example will be described.
実施例は、第1図のAおよびBに半導体装置と
その製造方法を述べる。第1図のAは基板1上に
1000℃、60分の熱酸化で酸化膜を形成し、その上
に厚さ4000Åに高濃度にリンが含まれた多結晶シ
リコンを堆積した後ホトレジスト加工技術によつ
てゲート絶縁膜2およびゲート電極3とを形成
し、その後不純物としてリンを加速電圧40keVで
1×1014cm-2イオン打込みして熱処理工程を経た
のち最終的な拡散深さ0.2μの低濃度領域4−1お
よび4−2と形成したところまでを示す。リン
は、後述するヒ素より拡散係数が大きいので、不
純物濃度勾配がゆるやかになる。 As an example, a semiconductor device and its manufacturing method will be described in FIGS. 1A and 1B. A in Figure 1 is on board 1.
An oxide film is formed by thermal oxidation at 1000°C for 60 minutes, and after depositing polycrystalline silicon containing a high concentration of phosphorus to a thickness of 4000 Å on the oxide film, the gate insulating film 2 and gate electrode are formed using photoresist processing technology. After that, 1×10 14 cm -2 ions were implanted as an impurity at an acceleration voltage of 40 keV, and after a heat treatment process, low concentration regions 4-1 and 4-2 with a final diffusion depth of 0.2 μ were formed. This shows the part where it is formed. Since phosphorus has a larger diffusion coefficient than arsenic, which will be described later, the impurity concentration gradient becomes gentler.
第1図のBは、その後の製造工程すなわち、ま
ず750℃の湿式酸化法によつて基板上に厚さ500Å
の酸化膜5−1および5−2を形成する。このと
き多結晶シリコン中に高濃度に不純物リンが含ま
れいるため、ゲート電極3の周辺には厚さ3000Å
の酸化膜5−3,5−4および5−5が形成され
る。すなわち、ゲート電極に対して自己整合的に
ゲート電極の側面に絶縁膜5−4及び5−5が形
成される。しかる後、絶縁膜5−4及び5−5を
マスクとして利用してヒ素を加速電圧150keVで
1×1016cm-2イオン打込みして熱処理工程を経た
のち最終的な拡散深さ0.4μの高濃度領域6−1お
よび6−2を形成したMOS型電界効果トランジ
スタが実現したところまでを示す。このときゲー
ト電極3と接する拡散層4−1および4−2が浅
く低濃度に形成されているため接合境界面の不純
物の濃度勾配がゆるやかとなりドレイン領域端で
動作バイアスによる電界集中が緩和された構造に
なつている。そのため素子の高耐圧化が実現され
ている。 B in Figure 1 shows the subsequent manufacturing process, i.e., first, a 500 Å thick film was formed on the substrate using a wet oxidation method at 750°C.
oxide films 5-1 and 5-2 are formed. At this time, since polycrystalline silicon contains a high concentration of impurity phosphorus, the area around the gate electrode 3 has a thickness of 3000 Å.
Oxide films 5-3, 5-4 and 5-5 are formed. That is, insulating films 5-4 and 5-5 are formed on the side surfaces of the gate electrode in a self-aligned manner with respect to the gate electrode. Thereafter, using the insulating films 5-4 and 5-5 as masks, arsenic is implanted with 1×10 16 cm -2 ions at an acceleration voltage of 150 keV, and after a heat treatment process, a final diffusion depth of 0.4 μm is formed. The realization of a MOS field effect transistor in which concentration regions 6-1 and 6-2 are formed is shown. At this time, since the diffusion layers 4-1 and 4-2 in contact with the gate electrode 3 are formed shallowly and with low concentration, the impurity concentration gradient at the junction interface is gentle, and the electric field concentration due to the operating bias at the edge of the drain region is alleviated. It's structured. Therefore, higher voltage resistance of the element has been realized.
以上説明したごとく本発明によれば、素子の高
耐圧化が実現し、チヤンネル長5μのMOS型電界
効果トランジスタにおいて、従来構造の素子耐圧
13.0Vが本構造によつて15.5Vとなり、20%近く
の高耐圧化が実現した。この改善分は素子を最大
8Vで使用した場合、素子特性の安定性あるいは
動作寿命が10倍以上向上したことに相当する。
As explained above, according to the present invention, a high breakdown voltage of the element is realized, and in a MOS field effect transistor with a channel length of 5μ, the breakdown voltage of the element of the conventional structure is
This structure reduces the voltage from 13.0V to 15.5V, achieving a nearly 20% increase in voltage resistance. This improvement will maximize the element
When used at 8V, this corresponds to an improvement of more than 10 times the stability of device characteristics or operating life.
更に本発明によれば、高耐圧構造の不純物分布
を形成するときにゲート電極を2回自己整合的に
使用し、高密度設計を実現する。すなわち、ゲー
ト電極を使用して不純物の導入を行うこととゲー
ト電極から自己整合的に形成された絶縁膜を使用
して不純物を導入するという2回の不純物導入に
よつて高密度設計を実現する。従来に比し、1/1.
5〜1/2のゲートエリアで実現できる。更に自己整
合的であるので、高耐圧化効果についてバラツキ
が低減できる均一な特性を実現できる。 Further, according to the present invention, when forming the impurity distribution of the high breakdown voltage structure, the gate electrode is used twice in a self-aligned manner, thereby realizing a high-density design. In other words, a high-density design is achieved by introducing impurities twice: by introducing impurities using a gate electrode and by introducing impurities using an insulating film formed in a self-aligned manner from the gate electrode. . 1/1 compared to before.
This can be achieved with a gate area of 5 to 1/2. Furthermore, since it is self-aligning, it is possible to achieve uniform characteristics that can reduce variations in the effect of increasing withstand voltage.
第1図A,Bは本発明を説明する断面図であ
る。
1……基板、2……ゲート絶縁膜、4−1,4
−2……低濃度領域、6−1,6−2……高濃度
領域。
FIGS. 1A and 1B are cross-sectional views illustrating the present invention. 1...Substrate, 2...Gate insulating film, 4-1, 4
-2...Low concentration area, 6-1, 6-2...High concentration area.
Claims (1)
クとして、第1の濃度の不純物を半導体基板表面
に注入して第1の不純物領域を形成した後、該ゲ
ート電極を酸化し、該酸化後のゲート電極をマス
クとして、該第1の濃度より大きい濃度の第2の
不純物を該基板表面に注入して、第1の不純物領
域より深い第2の不純物領域を形成することによ
り第1、第2の不純物領域からなるソース又はド
レイン領域を形成することを特徴とする半導体装
置の製造方法。 2 該ゲート電極が不純物を注入した多結晶シリ
コンより形成されてなることを特徴とする第1項
の半導体装置の製造方法。[Claims] 1. Using a gate electrode for a field effect transistor as a mask, impurities at a first concentration are implanted into the surface of a semiconductor substrate to form a first impurity region, and then the gate electrode is oxidized to form a first impurity region. Using the oxidized gate electrode as a mask, a second impurity having a concentration higher than the first concentration is implanted into the substrate surface to form a second impurity region deeper than the first impurity region. . A method of manufacturing a semiconductor device, comprising forming a source or drain region made of a second impurity region. 2. The method of manufacturing a semiconductor device according to item 1, wherein the gate electrode is formed of polycrystalline silicon into which impurities are implanted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11463687A JPS6323362A (en) | 1987-05-13 | 1987-05-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11463687A JPS6323362A (en) | 1987-05-13 | 1987-05-13 | Manufacture of semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15337376A Division JPS5378181A (en) | 1976-12-22 | 1976-12-22 | Semiconductor device and its manufacture |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6323362A JPS6323362A (en) | 1988-01-30 |
JPH0461497B2 true JPH0461497B2 (en) | 1992-10-01 |
Family
ID=14642775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11463687A Granted JPS6323362A (en) | 1987-05-13 | 1987-05-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6323362A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2888462B2 (en) * | 1991-08-26 | 1999-05-10 | 株式会社半導体エネルギー研究所 | Method for manufacturing insulated gate semiconductor device |
JPH0766393A (en) * | 1993-08-23 | 1995-03-10 | Nec Kansai Ltd | Manufacture of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5169985A (en) * | 1974-12-16 | 1976-06-17 | Hitachi Ltd | Handotaisochino seizohoho |
JPS6129554A (en) * | 1984-07-20 | 1986-02-10 | Nec Corp | Thermal printing head |
-
1987
- 1987-05-13 JP JP11463687A patent/JPS6323362A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5169985A (en) * | 1974-12-16 | 1976-06-17 | Hitachi Ltd | Handotaisochino seizohoho |
JPS6129554A (en) * | 1984-07-20 | 1986-02-10 | Nec Corp | Thermal printing head |
Also Published As
Publication number | Publication date |
---|---|
JPS6323362A (en) | 1988-01-30 |
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