JPS5842272A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the margin of design of a semiconductor device by a method wherein a polycrystalline Si layer formed on a thin oxide film and a thick oxide film on a semiconductor substrate is removed selectively, and selective oxidation is performed to the sides of polycrystalline Si layer and to the thin oxide film using the dielectric on the polycrystalline Si layer as the mask. CONSTITUTION:The polycrystalline Si layer 3 doped with phosphorus and a nitride film 4 are formed on the thick oxide film 1 and the thin oxide film 2 on the P type Si substrate 5, the layer and the film thereof are removed selectively, boron ions are implanted to form the high concentration P type regions 6. Selective oxidation 10' is performed using the nitride film 4 as the mask. Etching of oxide film is performed only in the perpendicular direction to the surface of substrate using the nitride film 4 as the mask to obtain openings 7, phosphorus is diffused through the openings thereof to form the semiconductor regions 8, and the wiring regions 9 are provided to complete. Accordingly the margin of design is reduced, and high integration can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an insulated gate field effect semiconductor device.

As an example of an insulated gate field effect conductor device currently in use, a silicon MO81C transistor is shown in FIG. Such silicon gate transistors are fast because the capacitance between the gate electrode, source, and drain is small. Furthermore, since so-called selective oxidation is used to prevent parasitic MO8, it has features such as a high degree of integration.

However, as can be easily seen from Figure 1.

A polysilicon interconnection process, source and drain contacts, and a selective oxidation process for preventing parasitic MO8 are formed by separate photoresist processes, and a certain design margin is required between each process. Therefore, there remains land for improvement for higher integration.

An object of the present invention is to provide a method for realizing an ultra-highly integrated MO8IC by reducing the design margin by forming insulating isolation regions for the gate wiring S, source, drain, and their contact portions in cell 7 alignment. be.

The basic structure of the present invention to achieve the above object includes a step of forming a first relatively thick oxide film on the surface of the first conductive type conductor substrate, and a step of forming a first relatively thick oxide film on the surface of the semiconductor substrate where no thick oxide film is formed. A process of selectively forming a relatively thin oxide film, a process of forming a polysilicon layer on the entire surface of these relatively thick oxide films and a relatively thin oxide film, a process of selectively removing this polysilicon layer, and a process of selectively removing this polysilicon layer. selectively oxidizing the semiconductor substrate under a relatively thin oxide film other than the sides of the polysilicon and under the polysilicon using the dielectric on the polysilicon layer as a mask;
The substrate under the relatively thin oxide film is oxidized.The oxide film is removed near the contact between the relatively thick oxide film and the relatively thin oxide film, and a window is formed so that the substrate contacts the polysilicon layer through the oxide film. The process of doing.

The method includes a step of forming source and drain regions of the second conductivity type through this window, and a step of taking out source and drain electrodes from this window.

Two embodiments of the present invention will be described below with reference to the drawings.

FIGS. 2(a) to 2(g) show the procedure of an embodiment according to the present invention. As shown in FIG. 2(a), a comparatively thick oxide film 1 is formed on the surface of a P-type semiconductor substrate using selective oxidation using a chemical film. Next, a relatively thin oxide film 2 is formed.

Next, polysilicon 3 doped with phosphorus is placed on oxide films 1 and 2.
Then, a chemical film 4 is formed. Figure 2(b) shows the X-X/
Corresponds to a cross-sectional view in the direction. Next, as shown in FIG. 2(e), the silicon dioxide film 4 and polysilicon 3 are selectively removed and boron ions are implanted.

A relatively high concentration P-type region 6 is formed. Next, Figure 2 (d
), selective oxidation is performed using the chemical film 4.

Next, as shown in FIG. 2(e), using the oxide film 4 as a mask, the window 7 can be opened by appropriately applying the oxide film to the entire surface, which progresses only in the direction perpendicular to the surface of the semiconductor substrate.

Next, diffuse phosphorus through window 7 as shown in Figure 2 (0).

N-type source and drain regions 8 are formed. Next, as shown in FIG. 2 (-), a wiring region 9 is formed and completed.

The effects of the present invention will be described below. As can be seen from the above embodiments, in the present invention, the insulating isolation region, the source and drain regions and their contact regions, and the gate polysilicon region are formed with full-pressure self-alignment lines. Moreover, the window 7 of the embodiment does not require the above Marsis, and depending on the processing of the oxide film and the accuracy of controlling the amount of chipping, it is possible to make the window 7 into an extremely fine turn of about several thousand λ. For this reason, an extremely compact transistor can be simply manufactured.

[Brief explanation of drawings]

Figure 1 shows typical silicone materials currently in use.
A cross-sectional view of an 8-type transistor is shown. Figure 2 (1) - 2nd
Figure (φ is a diagram showing an embodiment according to the present invention, and Figure 2 (a)
Figure 2(b) to Figure 2 (- is Figure 2 ((transformed)
3 is a cross-sectional view taken along line xx' according to the manufacturing process. In Figure 1, 1... relatively thick first oxide film, 2... relatively thin oxide film, 3...
Polysilicon layer, 4... Ch, chemical film, 5...
... P-type semiconductor substrate, 6 ... P-type isolation region, 7 ... window for forming source and drain and making contact, 8 ... n-type Source, drain region, 9... Wiring region, 10... Relatively thick second oxide film, 11... Oxide film. It is. U Figure 1 2nd Flash (fl) Bean paste? Evil (6) PJ Z diagram ((1)

Claims (1)

[Claims] a step of forming a polysilicon layer on a relatively thick oxide film and a relatively thin oxide film formed on the surface of a semiconductor substrate of a first conductivity type; a step of selectively removing the polysilicon layer; and a step of selectively removing the polysilicon layer. selectively oxidizing the side surface of the polysilicon layer and the semiconductor substrate under a relatively thin oxide film other than under the polysilicon layer using a dielectric on the polysilicon layer as a mask. Production method.