JPS6057970A - Manufacturer of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS semiconductor device of high reliability enabled to be formed in high density, in high integration and to act at a high speed by a method wherein high concentration diffusion regions are formed by introducing impurities of concentration higher than impurities introduced when a diffusion layer region is to be formed using a gate electrode and a film formed on the side wall thereof as masks. CONSTITUTION:After a gate oxide film 2 and a gate electrode 3 are formed on a P type substrate 1, phosphorus ions are implanted. Then a nitride film 5 is adhered, and when RIE is performed, the nitride film 5 are left on the side walls of the gate electrode 3. Then after a resist 6 is applied, the resist on a source and on the gate in the neighborhood of the source is removed. Then the nitride film 5 of the side wall part is removed using the resist as a mask, and when the resist is removed, the nitride film 5 is left at the gate side wall part of the drain side. Then when arsenic ions are implanted using the gate electrode 3 and the nitride film 5 of the gate side wall part as masks, a high concentration diffusion layer region 7 is formed by selfalignment with the gate electrode 3 on the source side, a low concentration diffusion layer region 4 is formed by selfalignment with the gate electrode 3 on the drain side, and a high concentration diffusion layer region 7 is formed by selfalignment at the position separated from the gate electrode 3.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method of manufacturing an MO8 type semiconductor device.

[Prior art and its problems]

With the increasing density, integration, and speed of conventional semiconductor devices,
MO8 type transistors have been miniaturized. In such a fine MO8 type transistor, so-called hot electrons are generated due to electric field concentration particularly near the drain, and the substrate current and gate current increase. These may cause a shift of the threshold of the transistor or a latch-up phenomenon in the complementary semiconductor device, thereby reducing the reliability of the semiconductor device.

Conventionally, these countermeasures include
T, I)■,)(L with low concentration diffusion layer near the drain)
(highly Doped Drain) structure, Gra
Transistors with a ded June tion structure have been proposed.

Although transistors with a graded junction structure suppress the above-mentioned drawbacks compared to conventional transistors, they have the disadvantage of increasing sheet channel effects. The LDD structure transistor suppresses the following drawbacks,
Although it can be said to be suitable for micro MO8 type transistors, it has an offset gate structure in which the highly doped source/drain region and the gate electrode region do not overlap, resulting in a reduction in the driving capability (fm) of the transistor due to parasitic resistance. . %, the offset structure with respect to the gate electrode on the source side has no effect on alleviating the electric field concentration near the drain, and only causes a decrease in the driving capability pm.

[Purpose of the invention]

The present invention improves the above-mentioned drawbacks of the conventional device, and aims to provide a method for manufacturing a semiconductor device that can achieve a high degree of integration, high integration, high speed, and is highly reliable in terms of %L.

[Summary of the invention]

This invention includes a process of forming a diffusion layer by introducing low-concentration impurities in a self-aligned manner with the electrode after forming the gate electrode, and a process of forming an insulating film or a conductive film other than a resist on the side walls of the gate. After applying the resist and patterning, a step of removing only one of the source/drain regions of the insulating film or the conductive film formed on the gate sidewall and removing the resist, and then removing the resist, and then removing the resist. This method of manufacturing a semiconductor device is characterized in that a highly concentrated impurity is introduced using a film formed on the gate electrode and its sidewalls as a mask to form a highly concentrated 1B-diffusion region.

〔Effect of the invention〕

By using this invention, the diffusion layer region on the drain side has a low concentration near the gate, making it possible to alleviate the electric field concentration on the drain side, similar to the conventional LDI structure transistor. The conventional LDD structure suppresses threshold shift due to hot electrons and increases in substrate current and gate current, and a high concentration diffusion layer region is formed on the source side in self-alignment with the gate electrode. The parasitic resistance can be reduced compared to the transistor shown in FIG.

Therefore, it is possible to create a highly reliable semiconductor device that is capable of high density, high integration, and high speed.

[Embodiments of the invention]

As an embodiment of the invention, a case will be described in which the invention is applied to an N-channel 11v10S transistor. As shown in Figure 1B, a gate oxide film 2 is formed on a P-type substrate 1.
After forming the gate electrode 3, phosphorus ions are implanted at a dose of 2×IQ13 cm'. As shown in Figure 1, when the nitride film 5 is deposited and IJ (IJ active ion etching) is performed, the nitride film 5 remains on the side walls of the gate electrode 3 (Figure 1C).・.

Next, after applying a resist 6, the resist near the source and gate is removed. Next, as shown in FIG. 1D, the nitride film 5 on the side wall portion is removed using the resist as a mask, and then the resist is removed. Then, the nitride film 5 remains on the gate sidewall portion on the drain side. Here gate electrode 3
Arsenic was applied 5X1 using the nitride film 5 on the gate sidewall as a mask.
Ions are implanted at a dose of 0 cm2. Then, Figure 1 d
As shown in , on the source side, a highly doped diffusion layer region 7 is formed in self-alignment with the gate electrode [3, and on the drain side, a low concentration diffusion layer region 4 is formed in self-alignment with the gate electrode i#li3. , a high concentration diffusion layer region 7 is formed at a position apart from the gate electrode 3 in an aligned manner. Next, as shown in Figure 1e, 0V
After depositing D8i0,8, contact holes are made,
Perform Al wiring, 1 wiring 9 for gate, 1 wiring for source side.
0, the drain side wiring 11 is formed.

In this case, the nitride film 5 deposited on the gate sidewall remains, but even if the nitride film 5 is removed after the ion implantation shown in FIG. good.

[Other embodiments of the invention]

Although the case where an insulating film is used for the gate sidewall portion has been described up to FIGS. 1A and 1E, it is also possible to use a conductive film. FIGS. 2a and 2b show a case in which a conductive film is used on the gate sidewalls. After the process shown in FIG. 1B, polycrystalline silicon 12 is deposited and oxidized in the summer after heating at 1000° C. for about 10'. When RIB is then performed, polycrystalline silicon 12 and oxide film 13 remain on the sidewalls of gate electrode 3. Thereafter, a resist is applied and patterned in the same manner as in FIG. 1C, and then the polycrystalline silicon and oxide film on the source side are removed. Thereafter, the resist is removed and arsenic ions are implanted at a high concentration to form a high concentration diffusion region 7. All you have to do is follow the steps in Figure 1e.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are sectional views explaining the present invention in detail, and FIGS. 2(a) and 2(b) are sectional views of other embodiments. In the figure, 1...P type substrate, 2.13... Oxide film, 3.12...
...Polycrystalline silicon, 4...Low concentration diffusion layer, 5...
Nitride film, 6... Resist, 7... High concentration diffusion layer, 8
...0VA) Sin. Membrane, 9, 10.11...A70 Agent Patent attorney Nori Chika Kensuke (1 other person) ＼ ＼

Claims (1)

[Claims] After forming the gate electrode, there is a step of introducing low concentration impurities in self-alignment with the gate electrode to form a low concentration diffusion layer, then a step of forming an insulating film or a conductive film other than resist on the side walls of the gate, and a step of applying resist and forming the gate. Unipatterning is performed to expose only either the source/drain side of the insulating film or conductive film formed on the sidewall, and after removing the insulating film or conductive film formed on the gate sidewall using the resist as a mask, the resist is removed. and a step of forming a high concentration diffusion layer by introducing impurities at a higher concentration than when forming the low concentration diffusion layer using a film formed on the gate electrode and its sidewall as a mask. A method for manufacturing a featured semiconductor device.