JPH0435224A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0435224A
JPH0435224A JP2137372A JP13737290A JPH0435224A JP H0435224 A JPH0435224 A JP H0435224A JP 2137372 A JP2137372 A JP 2137372A JP 13737290 A JP13737290 A JP 13737290A JP H0435224 A JPH0435224 A JP H0435224A
Authority
JP
Japan
Prior art keywords
input
gate
output
node
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2137372A
Other languages
English (en)
Japanese (ja)
Inventor
Yasuhiro Takai
康浩 高井
Yukio Fukuzou
福造　幸雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2137372A priority Critical patent/JPH0435224A/ja
Priority to US07/706,146 priority patent/US5095230A/en
Priority to EP91108737A priority patent/EP0459422A2/en
Publication of JPH0435224A publication Critical patent/JPH0435224A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP2137372A 1990-05-28 1990-05-28 半導体装置 Pending JPH0435224A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2137372A JPH0435224A (ja) 1990-05-28 1990-05-28 半導体装置
US07/706,146 US5095230A (en) 1990-05-28 1991-05-28 Data output circuit of semiconductor device
EP91108737A EP0459422A2 (en) 1990-05-28 1991-05-28 Data output circuit of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2137372A JPH0435224A (ja) 1990-05-28 1990-05-28 半導体装置

Publications (1)

Publication Number Publication Date
JPH0435224A true JPH0435224A (ja) 1992-02-06

Family

ID=15197147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2137372A Pending JPH0435224A (ja) 1990-05-28 1990-05-28 半導体装置

Country Status (3)

Country Link
US (1) US5095230A (cg-RX-API-DMAC7.html)
EP (1) EP0459422A2 (cg-RX-API-DMAC7.html)
JP (1) JPH0435224A (cg-RX-API-DMAC7.html)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469085A (en) * 1991-01-12 1995-11-21 Shibata; Tadashi Source follower using two pairs of NMOS and PMOS transistors
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors
JP2662559B2 (ja) * 1989-06-02 1997-10-15 直 柴田 半導体装置
JPH04192716A (ja) * 1990-11-26 1992-07-10 Mitsubishi Electric Corp Ｍｏｓトランジスタ出力回路
US5448181A (en) * 1992-11-06 1995-09-05 Xilinx, Inc. Output buffer circuit having reduced switching noise
SE504636C2 (sv) * 1995-07-27 1997-03-24 Ericsson Telefon Ab L M Universell sändaranordning
JP3070510B2 (ja) * 1997-03-21 2000-07-31 日本電気株式会社 半導体装置の入力回路および出力回路ならびに半導体装置
US6054881A (en) * 1998-01-09 2000-04-25 Advanced Micro Devices, Inc. Input/output (I/O) buffer selectively providing resistive termination for a transmission line coupled thereto
US6023176A (en) * 1998-03-27 2000-02-08 Cypress Semiconductor Corp. Input buffer
US6133757A (en) * 1998-07-16 2000-10-17 Via Technologies, Inc. High-speed and low-noise output buffer
US6512401B2 (en) * 1999-09-10 2003-01-28 Intel Corporation Output buffer for high and low voltage bus
DE10114159C2 (de) * 2001-03-22 2003-09-11 Infineon Technologies Ag Verfahren und Vorrichtung zur Datenübertragung
TWI238539B (en) * 2004-09-15 2005-08-21 Au Optronics Corp A signal transmitting system and method and an outputting signal driving device thereof
CN1588819B (zh) * 2004-09-28 2010-12-08 友达光电股份有限公司 信号传输系统与方法及其输出信号驱动装置
JP4882584B2 (ja) * 2006-08-07 2012-02-22 富士通セミコンダクター株式会社 入出力回路
CN113360449B (zh) * 2021-04-29 2022-12-27 山东英信计算机技术有限公司 一种服务器防护电路和服务器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02124634A (ja) * 1988-11-02 1990-05-11 Seiko Epson Corp ４値出力回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0720060B2 (ja) * 1985-08-14 1995-03-06 株式会社東芝 出力回路装置
US4829199A (en) * 1987-07-13 1989-05-09 Ncr Corporation Driver circuit providing load and time adaptive current

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02124634A (ja) * 1988-11-02 1990-05-11 Seiko Epson Corp ４値出力回路

Also Published As

Publication number Publication date
EP0459422A2 (en) 1991-12-04
US5095230A (en) 1992-03-10
EP0459422A3 (cg-RX-API-DMAC7.html) 1994-05-04

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