JPH04298045A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To limit the upward projection of a nitride film by subjecting an opening in the nitride film to anisotropic etching to form a side wall, and selectively form an oxide film of polycrystalline silicon. CONSTITUTION:A nitride film 21 is deposited on the entire surface of a substrate, and the nitride film 21 is subjected to anisotropic etching so that only a part 21a is left in the shape of side wall. Then, polycrystalline silicon 6 is selectively oxidized to form an oxide film 9, and polycrystalline base electrodes 6a and 6c have steep sides. The nitride side wall 21a limits the upward projection of a nitride film 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar semiconductor device.

0002

2. Description of the Related Art FIG. 2 is a sectional view showing a conventional method for manufacturing a bipolar semiconductor device disclosed in Japanese Patent Application Laid-Open No. 63-261746. In the figure, 1 is a P-type silicon substrate, 2 is an N+-type silicon substrate Buried diffusion layer, 3 is N- type epitaxial layer, 4 is element isolation oxide film, 5 is N for collector resistance reduction
+ type region, 6 is polycrystalline silicon, 6a and 6c are base electrode polycrystalline silicon, 6d is collector electrode polycrystalline silicon, 7 is nitride film, 9 is polycrystalline silicon oxide film, 10 is external base, 11 is intrinsic base, 12 is emitter, 13
14 is a metal electrode wiring, 14 is an inner wall oxide film, 15 is a CVD oxide film, 16 and 17 are polycrystalline silicon, 18 is an oxide film, 19
20 is a platinum silicide layer, 20 is a CVD oxide film, 30 is an emitter electrode, 31 is a base electrode, and 32 is a collector electrode. Note that in FIG. 2, some films are omitted to avoid complicating the drawing. Also, Figure 3 is Figure 2(c)
FIG. 6 is an enlarged view of the vicinity of the base and emitter regions for explaining in detail the steps between (f) and (f).

Next, the manufacturing process will be explained using FIG. 2. In FIG. 2(a), elements are separated by a well-known method, then polycrystalline silicon 6 of about 3000 angstroms is formed, the surface is oxidized to about 200 angstroms (not shown), and then a nitride film of 1000 to 2000 angstroms is formed. 7 is selectively formed in the portion where the base electrode and collector electrode are to be formed.

Next, as shown in FIG. 2(b), polycrystalline silicon 6 is selectively oxidized to form polycrystalline silicon 6a, 6c, and 6d.
form. 9 is an oxide film of polycrystalline silicon 6. Next, the nitride film 7 on the collector electrode is selectively removed, phosphorus ions are implanted into the collector electrode polycrystalline silicon 6d, and heat treatment is performed to form the N+ type region 5 for reducing collector resistance. Thereafter, boron ions of about 1 to 5 x 1015 cm-2 are implanted into the base electrode polycrystalline silicon 6a and 6c through the nitride film 7, and annealing is performed at a temperature of about 900°C. , 6c to make the boron concentration uniform.

Next, the emitter formation region 9b of the polycrystalline silicon oxide film 9 is selectively removed, and the inner wall is oxidized to form a second
An inner wall oxide film 14 having a thickness of approximately 0.00 angstroms is formed. Further, a P+ type external base 10 is formed by diffusion from the polycrystalline silicon 6a, 6c. This state is shown in FIG. 2(c) and FIG. 3(a).

[0006] Next, BF2 is 1 to 5 x 1013 cm-2
After forming the intrinsic base 11 by implanting ions to a certain extent, as shown in FIG. 2(d) and FIG. 3(b),
An oxide film 15 of about 0.00 angstroms and a polycrystalline silicon 16 of about 2000 angstroms are formed by CVD. Note that the CVD oxide film 15 is omitted in FIG. 2(d).

Next, the polycrystalline silicon 16 is etched using reactive ion etching, and the oxide films 14 and 1 are further etched.
5 was etched, as shown in Fig. 2(e) and Fig. 3(c).
Open the emitter as shown in . polycrystalline silicon 1
6 and the CVD oxide film 15 remain only on the sidewalls, and an emitter opening narrower than the opening of the nitride film 7 is opened in self-alignment, as shown in FIG. 3(c). At the same time, Fig. 2(e)
As shown in FIG. 2, the collector electrode polycrystalline silicon 6d is exposed.

Next, as shown in FIG. 3(d), polycrystalline silicon 17 of about 3000 angstroms is deposited on the entire surface, and the surface is oxidized to about 200 angstroms to form an oxide film 18, and then arsenic is added 1× 1016cm-2
ion implantation.

Next, as shown in FIG. 3(e), the oxide film 18, polycrystalline silicon 17, and nitride film 7 are etched.
Emitter 12 is formed in intrinsic base 11 by diffusion from polycrystalline silicon 17 by heat treatment.

Next, after removing the oxide film 18 on the surface of the polycrystalline silicon 17, platinum is deposited and heat treated to form a platinum silicide layer 19 on the surface of the polycrystalline silicon 17. Note that at this time, the thin oxide film is left on the resistor and other portions that are not to be silicided (not shown). Platinum remaining unreacted on the oxide film is removed with aqua regia, and then
As shown in FIG. 3(f), a CVD oxide film 20 is deposited on the entire surface.

Finally, as shown in FIG. 2(f), an emitter electrode 30, a base electrode 31, and a collector electrode 32 are formed, contact holes are opened, and metal electrode wiring 13 is formed.
Formation of

0012

[Problems to be Solved by the Invention] Conventional semiconductor devices are manufactured by the method described above, so due to the warpage of the nitride film when forming the polycrystalline silicon oxide film,
There was a problem in that the emitter opening had a high aspect ratio, resulting in large steps when forming wiring.

Furthermore, when forming the polycrystalline silicon oxide film, the oxide film sinks under the nitride film, so the shape of the polycrystalline silicon that remains after the oxide film is removed forms a gentle slope. However, when boron is diffused from the polycrystalline silicon to form an external base in a post-process, it is difficult to control the profile of the external base.

The present invention has been made to solve the above-mentioned problems, and provides a semiconductor device in which the warpage of the nitride film can be suppressed and the shape of polycrystalline silicon can be formed to have a steep slope. The purpose is to provide a manufacturing method.

[0015]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a sidewall of a nitride film in an opening of the nitride film by anisotropic etching, and then selectively oxidizing the polycrystalline film. This is to form a silicon oxide film.

[0016]

[Operation] The semiconductor device manufacturing method of the present invention forms a polycrystalline silicon oxide film using a nitride film with sidewalls as a mask, so it is possible to suppress warping of the nitride film and improve the shape of the polycrystalline silicon. can do.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which the same reference numerals as in FIGS. 2 and 3 indicate the same or corresponding parts, 8 is an oxide film, 21 is a nitride film, 21
a is a sidewall of the nitride film.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1(a), elements are separated by a well-known method, and then polycrystalline silicon 6 of approximately 3000 angstroms is formed, and the surface is
After forming an oxide film 8 by oxidation to a thickness of about 0 angstroms, a nitride film 7 of 1000 to 2000 angstroms is selectively formed on a portion where a base electrode is to be formed. The steps up to the step shown in FIG. 1(a) are the same as the conventional method.

Next, as shown in FIG. 1(b), a second nitride film 21 is deposited on the entire surface, and then the nitride film is anisotropically etched on the entire surface, thereby forming the structure shown in FIG. 1(c). As shown, only sidewall-shaped portions 21a of the nitride film 21 remain.

Next, as shown in FIG. 1(d), when the polycrystalline silicon 6 is selectively oxidized, a polycrystalline silicon oxide film 9 is formed, and the shape of the base electrode polycrystalline silicon 6a, 6c is inclined. formed into a steep shape. In addition, the nitride film 7
The warpage of the nitride film is also suppressed by the sidewall 21a of the nitride film. Next, the base electrode polycrystalline silicon 6a,
Boron is applied to 6c through the nitride film 7 to a thickness of 1 to 5 x 1015 cm.
-2 ion implantation is performed, annealing is performed at a temperature of approximately 900°C, and base electrode polycrystalline silicon 6a, 6c is formed.
Equalize the boron concentration inside.

As shown in FIG. 1E, the emitter forming region of the polycrystalline silicon oxide film 9 is selectively removed, and the inner wall is oxidized to form an inner wall oxide film 14 of about 200 angstroms. Further, a P+ type external base 10 is formed by diffusion from the polycrystalline silicon 6a, 6c. Next, BF2 is ion-implanted to about 1 to 5 x 1013 cm-2 to form an intrinsic base 11, and then
An oxide film 15 of about 0 angstroms and a polycrystalline silicon 16 of about 2000 angstroms are formed by CVD.

Next, the polycrystalline silicon 16 is etched using reactive ion etching, and the oxide film 14,
Etching step 15 is performed to form an emitter opening as shown in FIG. 1(f). Polycrystalline silicon 16 and CVD oxide film 15 remain only on the sidewalls, and an emitter opening narrower than the opening in nitride film 7 is opened in self-alignment.

Next, polycrystalline silicon 17 of about 3000 angstroms is deposited on the entire surface, and the surface is oxidized to about 200 angstroms to form an oxide film, and then arsenic ions of about 1×10 16 cm −2 are implanted. Next, the oxide film, polycrystalline silicon 17, and nitride film 7 are etched, and an emitter 12 is formed in the intrinsic base 11 by diffusion from the polycrystalline silicon 17 by heat treatment.

Next, after removing the oxide film on the surface of the polycrystalline silicon 17, platinum is deposited and heat treated to form a platinum silicide layer 19 on the surface of the polycrystalline silicon. The unreacted platinum remaining on the oxide film was removed with aqua regia, and then a CVD oxide film 20 was deposited on the entire surface as shown in Figure 1(g).
Deposit.

[0025]

As described above, according to the semiconductor manufacturing method according to the present invention, when polycrystalline silicon is oxidized, a sidewall of the nitride film is formed at the edge of the nitride film, so that the nitride film This has the effect of suppressing the warpage of the substrate and reducing the difference in level between the base layers during wiring formation in a later process. In addition, the existence of the sidewalls of the nitride film suppresses the penetration of the polycrystalline silicon oxide film into the polycrystalline silicon, resulting in the shape of the polycrystalline silicon having a steep slope. This has the effect of making it easier to control the profile when diffusing to form an external base.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 3 is an enlarged sectional view of the vicinity of the base and emitter regions for explaining the steps between FIGS. 2(c) to 2(f) in detail.

[Explanation of symbols]

1 P- type silicon substrate 2 N+ type buried diffusion layer 3 N- type epitaxial layer 4
Element isolation oxide film 5 N+ type region for reducing collector resistance 6
Polycrystalline silicon 6a Base electrode polycrystalline silicon 6b Base electrode polycrystalline silicon 6d Collector electrode polycrystalline silicon 7 Nitride film 8 Oxide film 9 Polycrystalline silicon oxide film 10 External base 11 Intrinsic base 12 Emitter 13 Metal electrode wiring 14 Inner wall oxide film 15 CVD oxide film 16 Polycrystalline silicon 17 Polycrystalline silicon 18 Oxide film 19 Platinum silicide layer 20 CVD oxide film 21 Nitride film 21a Nitride film sidewall

Claims (1)

[Claims] 1. A first polycrystalline silicon is deposited on one main surface of a silicon substrate having an island region of a first conductivity type, and a first oxidation-resistant film is formed on a selected surface of the polycrystalline silicon. forming a second oxidation-resistant film on the entire surface and leaving the second oxidation-resistant film only on the sidewalls of the first oxidation-resistant film by anisotropic etching; A first polycrystalline silicon oxide film is formed by selectively oxidizing the polycrystalline silicon using the first oxidation-resistant film as a mask, and at least a portion of the remaining first polycrystalline silicon is coated with the first oxidation-resistant film. a step of introducing a second conductivity type impurity through the oxidizing film; a step of selectively removing a portion of the first polycrystalline silicon oxide film to expose a portion of the island region; forming a thin oxide film on the surface of the island region and the sidewalls of the first polycrystalline silicon, and forming a first region of the second conductivity type on the unexposed island region; a step of introducing a second conductivity type impurity into the island region to form a second conductivity type second region extending into the first region;
A step of forming a VD oxide film and a second polycrystalline silicon, and leaving the second polycrystalline silicon only on the side wall portion of the removed region of the first polycrystalline silicon oxide film by etching, and a step of forming the exposed first CVD oxide film. etching the oxide film and the thin oxide film to expose the second region of the second conductivity type, selectively forming a third polycrystalline silicon, and forming the first conductivity type from the third polycrystalline silicon; a step of diffusing type impurities to form a third region of the first conductivity type within the second region of the second conductivity type; a step of forming a metal silicide layer on the surface of the third polycrystalline silicon; 1. A method of manufacturing a semiconductor device, comprising: step of forming a second CVD oxide film.