JPH04246833A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the deterioration in characteristics due to heat carriers by a method wherein high and low concentration impurity diffused regions are selfmatchingly formed by one time ion-implantation step while a part of a gate electrode is overlapped with the part above the low concentration impurity diffused region so as to decrease the field intensity. CONSTITUTION:A coating film 8 is left only on the parts below the sides of stepped part of a polycrystal silicon layer 3 so as to remove all the other parts of the coating film 8. Next, the whole surface is anisotropically etched away by RIE step to remove the surface of a silicon oxide film 6, the coating film 8 and a polycrystal silicon film 3 so that the surface of a gate oxide film 2 may be just exposed to form a gate electrode 3a having oblique parts taking copied sectional shape after that of the coating film 8 on the stepped parts of the polycrystal silicon layer 3. Finally, low concentration impurity diffused regions 5 and high concentration impurity diffused regions 6 are formed beneath the oblique parts of the gate electrode 3a by ion-implanting phosphorus or arsenic using the gate electrode 3a as a mask.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an insulated gate field effect transistor.

0002

2. Description of the Related Art As semiconductor devices become more sophisticated and more highly integrated, the problem of deterioration of characteristics of insulated gate field effect transistors due to hot carriers has become apparent. In order to reduce the device area, it is necessary to dope the source/drain region with a high concentration of impurity, which increases the electric field strength and generates hot carriers, which are trapped in the gate insulating film and have an apparent This is a phenomenon in which changing the upper threshold voltage causes deterioration of characteristics.

Conventionally, as a technique to avoid this phenomenon, a low concentration impurity diffusion region of the same conductivity type is formed around a high concentration impurity diffusion region by utilizing the difference in diffusion coefficient between phosphorus and arsenic to alleviate the electric field. The method to do this is DDD (Double
This is known as a Diffused Drain structure. In addition, LDD (L
(lightly doped drain) structure is known.

On the other hand, as a means of alleviating the electric field, a method has been proposed in which the impurity concentration in the low concentration impurity diffusion region is kept constant and the gate electrode is arranged directly above it.
Technical Digest International Electron Devices Meeting (Technic
al Digest International
lElectron Devices Meeti
ng) 1986, pp. 742-745 and technical
Digest International Electron Devices Meeting (Technical Digest)
gest International Elec
tron Devices Meeting)19
1987, pp. 38-41}.

FIGS. 3A to 3C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 3A, a gate oxide film 2 is provided on the surface of a P-type silicon substrate 1 provided with an element formation region, and a polycrystalline silicon layer 3 and a silicon oxide film are formed on the gate oxide film 2. 6 are sequentially deposited and provided. Next, the upper surfaces of the silicon oxide film 6 and the polycrystalline silicon layer 3 are selectively and sequentially etched to leave a portion of the thickness of the polycrystalline silicon layer 3. Next, using the silicon oxide film 6 and the polycrystalline silicon layer 3 directly under the silicon oxide film 6 as masks, phosphorus ions are implanted into the silicon substrate 1 at a low concentration to form an N-type low concentration impurity diffusion region 5.

Next, as shown in FIG. 3(b), a silicon oxide film 7 is deposited over the entire surface.

Next, as shown in FIG. 3C, the entire surface is etched back, leaving the silicon oxide film 7 only on the side surface of the polycrystalline silicon layer 3 directly under the silicon oxide film 6, and forming the side wall portion 7a.
is formed, and the planar silicon oxide film 7 and polycrystalline silicon layer 3 are removed to form a gate electrode 3a. Next, arsenic ions are implanted at a high concentration using the gate electrode 3a and the side wall portions 7a as masks to form an N-type high concentration impurity diffusion region 4 connected to the low concentration impurity diffusion region 5, and the LDD
Form source/drain regions of the structure.

[0009]

[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, two steps are required to form a low concentration impurity diffusion region and a high concentration impurity diffusion region for relaxing the electric field.
It required multiple ion implantations. Furthermore, in order to form a part of the gate electrode directly above the low concentration impurity diffusion region,
There is a problem in that it is necessary to stop the etching of the polycrystalline silicon layer midway through, and controlling the thickness of this remaining film greatly affects the impurity distribution.

0010

[Means for Solving the Problems] A first method for manufacturing a semiconductor device of the present invention is to form a gate insulating film on a semiconductor substrate of one conductivity type in which an element formation region is formed, and to cover the gate insulating film with a polycrystalline polycrystalline film. a step of sequentially depositing a silicon layer and an insulating film;
a step of selectively and sequentially etching the upper surfaces of the insulating film and the polycrystalline silicon layer to leave a portion of the thickness of the polycrystalline silicon layer to form a stepped portion; and a step of providing a mask layer only on the stepped portion to cover the entire surface. A step of etching back and forming a gate electrode having an inclination that mirrors the shape of the mask layer in the stepped portion and removing other portions of the polycrystalline silicon layer, and using the gate electrode as a mask, impurities of opposite conductivity type are added to the semiconductor substrate. ion implantation to form a low concentration impurity diffusion region of a reverse conductivity type directly under the slope portion and a high concentration impurity diffusion region of a reverse conductivity type connected to the low concentration impurity diffusion region. .

A second method for manufacturing a semiconductor device of the present invention includes:
A gate insulating film is formed on the one conductivity type semiconductor substrate on which the element formation region is formed, a polycrystalline silicon film is deposited on the gate insulating film, and a gate electrode is formed by selectively etching the polycrystalline silicon layer. a step of depositing a thin polycrystalline silicon layer and an insulating film on the surface including the gate electrode and etching it back to form a sidewall portion by leaving only on the side surface of the gate electrode; etching away the insulating film to leave the thin polycrystalline silicon layer on the side surface and vicinity of the gate electrode; and ion-implanting impurities of opposite conductivity type into the semiconductor substrate using the gate electrode and the thin polycrystalline silicon layer as a mask. The method includes the step of forming a low concentration impurity diffusion region of an opposite conductivity type directly under the thin polycrystalline silicon layer and a high concentration impurity diffusion region connected to the low concentration impurity diffusion region.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a gate oxide film 2 is formed by thermally oxidizing the surface of a P-type silicon substrate 1 on which an element formation region is formed, and a gate oxide film 2 is formed on the gate oxide film 2 to a thickness of 0. ．．
Polycrystalline silicon layer 3 of 5-0.8 μm and thickness 0.3 μm
m silicon oxide films 6 are sequentially deposited. Next, the upper surfaces of the silicon oxide film 6 and the polycrystalline silicon layer 3 are selectively and sequentially etched so that the thickness of the polycrystalline silicon layer 3 is 0.1 μm.
Etching is stopped when it reaches a certain level.

Next, as shown in FIG. 1(b), a coating film 8 such as a silica film or an organic film is applied by a spin coating method and the entire surface is etched back to remove the side surface of the stepped portion of the polycrystalline silicon layer 3. The coating film 8 is left only in the lower part and the other coating film 8 is removed. Here, the coating film 8 is formed at a solid content concentration of 3 to 6% and a coating rotation speed of 3500 to 5000 rpm.

Next, as shown in FIG. 1(c), the entire surface is R
The upper surface of the silicon oxide film 6, the coating film 8, and the polycrystalline silicon layer are etched and removed by anisotropic etching using an IE (reactive ion etching) method so that the surface of the gate oxide film 2 is just exposed; A gate electrode 3a having an inclined portion mirroring the cross-sectional shape of the coating film 8 is formed in a stepped portion of the polycrystalline silicon layer 3. Next, using the gate electrode 3a as a mask, phosphorus or arsenic ions are implanted into the silicon substrate 1 directly under the sloped portion of the gate electrode 3a, into the low concentration impurity diffusion region 5, and into the silicon substrate 1 connected to the low concentration impurity diffusion region 5. A source/drain region having a high concentration impurity diffusion region 4 is formed.

FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2(a), after depositing a polycrystalline silicon layer 3 to a thickness of 0.5 to 0.8 μm on the gate oxide film 2 by the same process as in the first embodiment, , selectively etching the polycrystalline silicon layer 3 to form a gate electrode 3a.
form. Next, on the surface including the gate electrode 3a, 20 to 5
A polycrystalline silicon layer 9 with a thickness of 0 nm is deposited, and a silicon nitride film 10 is formed on the polycrystalline silicon layer 9 as a gate electrode 3a.
deposits to a similar thickness.

Next, as shown in FIG. 2(b), the silicon nitride film 10 and the polycrystalline silicon layer 9 are etched back.
Sidewall portions 10a are formed leaving silicon nitride film 10 and polycrystalline silicon layer 9 only on the side surfaces of gate electrode 3a, and other portions of silicon nitride film 10 and polycrystalline silicon layer 9 are removed.

Next, as shown in FIG. 2(c), the side wall portion 1
The silicon nitride film 10 of 0a is removed by etching, and phosphorus or arsenic ions are implanted into the silicon substrate using the gate electrode 3a as a mask to form an N-type low concentration impurity diffusion region 5 directly under the polycrystalline silicon layer 9 and low concentration impurity diffusion. A high concentration impurity diffusion region 4 connected to region 5 is formed.

In the second embodiment, the number of steps is increased in some steps compared to the first embodiment, but there is an advantage that the margin for etching the sidewall portion is increased and the dimensions of the source/drain regions can be easily controlled.

[0022]

[Effects of the Invention] As explained above, the present invention provides source and
To form the drain region, a high-concentration impurity diffusion region and a low-concentration impurity diffusion region can be formed in a self-aligned manner in a single ion implantation process, and a portion of the gate electrode overlaps directly above the low-concentration impurity diffusion region, which reduces the electric field. Since the strength can be relaxed, an insulated gate field effect transistor with less characteristic deterioration due to hot carriers can be manufactured in a simple process with good controllability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 Gate oxide film 3 Polycrystalline silicon layer 3a Gate electrode 4 High concentration impurity diffusion region 5 Low concentration impurity diffusion region 6,7 Silicon oxide film 7a Side wall part 8 Coating film 9 Polycrystalline silicon layer 10 Silicon nitride layer 10a Side wall part

Claims (2)

[Claims] 1. A step of forming a gate insulating film on a semiconductor substrate of one conductivity type in which an element formation region is formed, and sequentially depositing a polycrystalline silicon layer and an insulating film on the gate insulating film,
a step of selectively and sequentially etching the upper surfaces of the insulating film and the polycrystalline silicon layer to leave a portion of the thickness of the polycrystalline silicon layer to form a stepped portion; and a step of providing a mask layer only on the stepped portion to cover the entire surface. A step of etching back and forming a gate electrode having an inclination that mirrors the shape of the mask layer in the stepped portion and removing other portions of the polycrystalline silicon layer, and using the gate electrode as a mask, impurities of opposite conductivity type are added to the semiconductor substrate. ion implantation to form a low concentration impurity diffusion region of a reverse conductivity type directly under the slope portion and a high concentration impurity diffusion region of a reverse conductivity type connected to the low concentration impurity diffusion region. A method for manufacturing a semiconductor device. 2. A step of forming a gate insulating film on a semiconductor substrate of one conductivity type in which an element formation region is formed, depositing a polycrystalline silicon film on the gate insulating film, and selectively depositing the polycrystalline silicon layer. a step of etching to form a gate electrode; and a step of depositing a thin polycrystalline silicon layer and an insulating film on the surface including the gate electrode and etching back to form a side wall portion by leaving only on the side surfaces of the gate electrode. , a step of etching away the insulating film on the side wall portion to leave the thin polycrystalline silicon layer on the side surface and vicinity of the gate electrode, and etching the semiconductor substrate with a reverse conductivity type using the gate electrode and the thin polycrystalline silicon layer as a mask A step of ion-implanting impurities to form a low concentration impurity diffusion region of an opposite conductivity type and a high concentration impurity diffusion region connected to the low concentration impurity diffusion region directly under the thin polycrystalline silicon layer. A method for manufacturing a semiconductor device.