JPH0427022B2 - - Google Patents

Info

Publication number
JPH0427022B2
JPH0427022B2 JP62006388A JP638887A JPH0427022B2 JP H0427022 B2 JPH0427022 B2 JP H0427022B2 JP 62006388 A JP62006388 A JP 62006388A JP 638887 A JP638887 A JP 638887A JP H0427022 B2 JPH0427022 B2 JP H0427022B2
Authority
JP
Japan
Prior art keywords
layer material
inner layer
stacked body
board
caulking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62006388A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63173624A (ja
Inventor
Yoshinori Urakuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62006388A priority Critical patent/JPS63173624A/ja
Publication of JPS63173624A publication Critical patent/JPS63173624A/ja
Publication of JPH0427022B2 publication Critical patent/JPH0427022B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Landscapes

  • Laminated Bodies (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP62006388A 1987-01-14 1987-01-14 多層板の製造方法 Granted JPS63173624A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62006388A JPS63173624A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62006388A JPS63173624A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Publications (2)

Publication Number Publication Date
JPS63173624A JPS63173624A (ja) 1988-07-18
JPH0427022B2 true JPH0427022B2 (enrdf_load_stackoverflow) 1992-05-08

Family

ID=11636993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62006388A Granted JPS63173624A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Country Status (1)

Country Link
JP (1) JPS63173624A (enrdf_load_stackoverflow)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56131995A (en) * 1980-03-18 1981-10-15 Matsushita Electric Works Ltd Method of producing multilayer printed circuit board
JPS61131595A (ja) * 1984-11-30 1986-06-19 三菱電機株式会社 多層プリント配線板の製造方法
JPS63153895A (ja) * 1986-12-17 1988-06-27 東芝ケミカル株式会社 多層配線板の製造方法

Also Published As

Publication number Publication date
JPS63173624A (ja) 1988-07-18

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees