JPH0427023B2 - - Google Patents

Info

Publication number
JPH0427023B2
JPH0427023B2 JP62006389A JP638987A JPH0427023B2 JP H0427023 B2 JPH0427023 B2 JP H0427023B2 JP 62006389 A JP62006389 A JP 62006389A JP 638987 A JP638987 A JP 638987A JP H0427023 B2 JPH0427023 B2 JP H0427023B2
Authority
JP
Japan
Prior art keywords
press
pin
caulking
fit
layer material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62006389A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63173623A (ja
Inventor
Yoshinori Urakuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62006389A priority Critical patent/JPS63173623A/ja
Publication of JPS63173623A publication Critical patent/JPS63173623A/ja
Publication of JPH0427023B2 publication Critical patent/JPH0427023B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Landscapes

  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
JP62006389A 1987-01-14 1987-01-14 多層板の製造方法 Granted JPS63173623A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62006389A JPS63173623A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62006389A JPS63173623A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Publications (2)

Publication Number Publication Date
JPS63173623A JPS63173623A (ja) 1988-07-18
JPH0427023B2 true JPH0427023B2 (enrdf_load_stackoverflow) 1992-05-08

Family

ID=11637018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62006389A Granted JPS63173623A (ja) 1987-01-14 1987-01-14 多層板の製造方法

Country Status (1)

Country Link
JP (1) JPS63173623A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241893A (ja) * 1988-03-24 1989-09-26 Alps Electric Co Ltd 金属ベース積層板の製造方法
GB0614087D0 (en) 2006-07-14 2006-08-23 Airbus Uk Ltd Composite manufacturing method
CN105392304B (zh) * 2015-10-21 2017-12-05 胜宏科技(惠州)股份有限公司 一种线路板压合方法

Also Published As

Publication number Publication date
JPS63173623A (ja) 1988-07-18

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