JPH0421222B2 - - Google Patents

Info

Publication number
JPH0421222B2
JPH0421222B2 JP57181125A JP18112582A JPH0421222B2 JP H0421222 B2 JPH0421222 B2 JP H0421222B2 JP 57181125 A JP57181125 A JP 57181125A JP 18112582 A JP18112582 A JP 18112582A JP H0421222 B2 JPH0421222 B2 JP H0421222B2
Authority
JP
Japan
Prior art keywords
bank
cache
memory
cache memory
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57181125A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5971184A (ja
Inventor
Mamoru Umemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57181125A priority Critical patent/JPS5971184A/ja
Publication of JPS5971184A publication Critical patent/JPS5971184A/ja
Publication of JPH0421222B2 publication Critical patent/JPH0421222B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57181125A 1982-10-15 1982-10-15 記憶装置 Granted JPS5971184A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57181125A JPS5971184A (ja) 1982-10-15 1982-10-15 記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57181125A JPS5971184A (ja) 1982-10-15 1982-10-15 記憶装置

Publications (2)

Publication Number Publication Date
JPS5971184A JPS5971184A (ja) 1984-04-21
JPH0421222B2 true JPH0421222B2 (enrdf_load_stackoverflow) 1992-04-09

Family

ID=16095295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57181125A Granted JPS5971184A (ja) 1982-10-15 1982-10-15 記憶装置

Country Status (1)

Country Link
JP (1) JPS5971184A (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
JPH0670773B2 (ja) * 1984-11-01 1994-09-07 富士通株式会社 先行制御方式
JPS61267149A (ja) * 1985-05-21 1986-11-26 Nec Corp デ−タ処理装置
JPH0746324B2 (ja) * 1987-08-12 1995-05-17 株式会社日立製作所 情報処理装置
JP4656862B2 (ja) * 2004-05-28 2011-03-23 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
JPS5971184A (ja) 1984-04-21

Similar Documents

Publication Publication Date Title
US5390308A (en) Method and apparatus for address mapping of dynamic random access memory
US5450564A (en) Method and apparatus for cache memory access with separate fetch and store queues
US5251310A (en) Method and apparatus for exchanging blocks of information between a cache memory and a main memory
JPS60157646A (ja) メモリバンク切換装置
US5293622A (en) Computer system with input/output cache
JP2561261B2 (ja) バッファ記憶アクセス方法
US5983313A (en) EDRAM having a dynamically-sized cache memory and associated method
JPH0421222B2 (enrdf_load_stackoverflow)
JPH0282330A (ja) ムーブアウト・システム
JPH1165925A (ja) 情報処理装置
JP2002041358A (ja) プロセッサシステム
US5933856A (en) System and method for processing of memory data and communication system comprising such system
JPS5847784B2 (ja) キ−記憶システム
JPH1055308A (ja) キャッシュメモリ
JPH0573420A (ja) キヤツシユメモリを持つコンピユータ
JPH087663B2 (ja) コンピユータ・システムおよびその記憶装置アクセス方法
US7840757B2 (en) Method and apparatus for providing high speed memory for a processing unit
JP2502406B2 (ja) 記憶制御方式およびデ―タ処理装置
JPH0652056A (ja) キャシュメモリシステム
JPH0793215A (ja) 半導体記憶装置
JPH0877072A (ja) キャッシュメモリ装置
JPH04359336A (ja) キャッシュメモリのデータ置換回路
JPH0243692A (ja) マイクロプロセッサ及びそのキャッシュメモリ
JPH0573419A (ja) 仮想記憶装置
JPS6243737A (ja) 割り込み制御方式