JPH04190444A - Bus interface device - Google Patents

Abstract

PURPOSE:To decrease the scale of a bus interface circuit while increasing the transfer speed by providing a data register as a FIFO circuit of several times performance and performing its transfer in bi-direction, and providing a controller with a FIFO circuit clearing function. CONSTITUTION:When data are transferred from a 1st central processing unit 1 to a 2nd central processing unit 8, the address of a FIFO controller 11 is specified through an address bus 2 and a write signal is outputted from a control bus 4 to the FIFO controller 11. The FIFO controller 11 outputs a signal indicating the transfer direction of the FIFO circuit to a FIFO circuit 5a through a signal line 10. When data are transferred from the 2nd central processing unit 8 to the 1st central processing unit 1, reverse operation is performed. Further, the FIFO controller 11 is provided with the function for clearing the contents of the FIFO circuit 5a. Thus, the transfer speed is improved, the scale of the bus interface circuit is decreased, and transfer is started normally after an accident.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus interface device that is particularly intended to improve transfer speed and transfer accuracy in a microcomputer system having two central processing units.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional bus interface circuit. In the figure, a first central processing unit 1 is connected to a data register 5 and a status register 6 via an address bus 2, a data bus 3, and a control bus 4.

Data register 5 and status register 6 are connected to port 7 via address bus 2, data bus 3, and control bus 4. On the other hand, the second central processing unit 8 is connected to the baud 7 via an address bus 2, a data bus 3, and a control bus 4.

Next, the operation will be explained. first central processing unit)
When transferring data from to the second central processing unit 8, the first central processing unit m1 specifies the address range of the status register 6 via the address bus 2, outputs the read number 2 from the control bus 4, and By loading the contents of the status register 6 into the data bus 3, the state of the data bus 5 is checked. The status register is a register that indicates the presence or absence of data in the data register 5. If there is no data in the data register 5, the bit indicating the presence or absence of data in the status register 6 is cleared, and the first central processing unit 1 The address of the data register 5 is designated by the address bus 2, a write signal is output to the control bus 4, data is output to the data bus 3, and one byte of data is written to the data register 5. At this time, a signal is output from the data register 5 to the status register 6 via the signal MA9, and a pit indicating the presence or absence of status/dystero data is set. The first central processing unit 1 constantly monitors the status of the status register 6, and stops writing to the data register 5 when the status register 6 is set. The second central processing unit 8 also monitors the status of the status register 6, and when the status register 6 is set, it specifies the address of the data register 5 via the address bus 2 and sends the address to the control/roll bus 4. It outputs a read signal and takes in 1 byte of data from the data register 5 via the data bus 3. At this time, a signal is output from the data register 5 via the signal line A9, and the status register 6 is cleared. When data is transferred from the second central processing unit 8 to the first central processing unit 1, the operation is reversed to that described above.

[Problem to be solved by the invention]

Conventional bus interface circuits were configured as described above, so data transfer between central processing units was performed in one step.
Since it can only be performed byte by byte, there is a problem that the transfer speed cannot be improved, and if the transfer is interrupted due to an accident during the transfer, the data will remain in the data register and the next transfer will not be successful. The problem was that it was not possible to do so.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a bus interface circuit that improves the data transfer speed and transfer accuracy between central processing units. .

[Means to solve the problem]

A bus interface circuit according to the present invention includes a FIFO circuit having a data register of several bytes, a FIFO controller, a FIFO status register, a central processing unit, an address bus, a data bus, a control bus, and a port. The central processing unit connects the FIFO circuit, FIFO controller,
The FIFO status register is connected to the FIFO controller via the address bus, to the FIFO status register via the control bus, and to the FIFO status register via the control bus.

The FIFO circuit is connected to the port via a data bus. The FIFO controller is connected to ports via an address bus and a control bus. And FIF
The O status register is connected via an address bus, a data bus, and a control bus.

[Effect]

The bus interface device according to the present invention uses a FIFO circuit having several byte data registers instead of a 1-byte data register, so data can be transferred in batches between central processing units, resulting in improved transfer speed. Furthermore, since the FIFO controller is equipped with a function to clear the contents of the FIFO circuit, even if the transfer is interrupted due to an accident, the next transfer can be started normally.

Furthermore, since the transfer direction of the F[FO circuit can be set, the scale of the bus interface circuit can be halved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a bus ink-face circuit according to an embodiment of the present invention. In the figure, the first central processing value @1 is sent to the FIFO controller 11, the FIFO status data, and the FIFO 6a via the atto L bus 2.
FIFO circuit 5a via data bus 3.

FIFO collection) - to the roller 11 and the FIFO stator data nosta 6a, and via the control bus 4 to the FIFO
O controller 11, F[FO status register 6a
is connected to. FIFO circuit 5a is connected to port 7 via data bus 3. FIFO controller 1
1 is connected to port 7 via address bus 2 and control bus 4. Then, the FIFO status register 6a is address bus 2, address bus 0 71 bus 4
It is connected to port 7 via. The FIFO circuit 5a and the FIFO controller 11 are connected via a signal line BIO. The FIFO controller 11 and the FIFO status register 6a are connected via a signal line A9. The second central processing unit 8 is connected to the address bus 2, data bus 3, and control bus 4 via the port 7.

Next, the operation will be explained. First central processing value N1
When data is transferred from the first central processing unit 8 to the second central processing unit 8, the first central processing value W1 is transferred to the F
Specify the address of the IFO controller 11, and send the write signal from the Kono)/Low) L bus 4 to the FIFO controller 1.
Output to 1. Signal 1B from FIFO controller 11
A signal instructing the transfer direction of the FIFO circuit is output to the FIFO circuit 5a via the FIFO circuit 10. In the current example, the first
Since data is transferred from the central processing unit 1 to the second central processing value M8, the transfer direction of the FIFO circuit is the first
from the central processing unit 1 to the second central processing value w8. The first central processing unit 1 specifies the address of the FIFO status register 6a via the address bus 2, and performs a readout via the core control bus 4.
The state of the FIFO circuit 5a is checked by outputting the signal to the FIFO status register 6a and importing the contents of the FIFO status register 6a into the data bus 3.

The FIFO status register 6a is the FIFO circuit 5a.
It has a function to detect the presence or absence of data and the number of remaining bytes. If there is no data in the FIFO circuit 5a or if there is space, the first central processing unit 1 specifies the address of F+FO controller 11 to be sent to the bus 2 and writes it to the controller 1-roll bus 4. By outputting the signal, a write signal is output from the FIFO controller 11 to the FIFO circuit 5a via the bus BIO.
Data is output to the data bus 3, and data corresponding to the empty bytes of the FIFO circuit 5a is taken in. At this time, FIF
From O controller 11 to A: via line A9, FIF
O status, signal is output to distalo a, FIF
A bit indicating the presence or absence of data in the O status register 6a is set to 1. The first central processing unit 1 is always F
Monitor the status of IFO status register 6a)
When the FIFO status register 6a is set, writing to the FIFO circuit 5a'' is stopped.The second central processing unit 8 also monitors the state of the FIFO status register 6a, and the FIFO status register 6a is set. When the bit indicating the presence or absence of data in the register 6a is set, the FIFO controller 1 is
1's Ti position is determined, and a readout signal is output to the control bus 4. The FI that received this read signal
The FO controller 1 to the roller 11 are connected to Fi through the signal line Boo.
Readout 1. to FO circuit 5a. (outputs number g. Then, the data in the FIFO circuit 5a is taken into the central processing unit 8.

At this time, the FIFO controller 11 outputs a signal to the FIFO status register 6a via the line A9,
Clear the pin indicating the presence or absence of data in the FIFO status register 6a. After that, repeat the above operation. When data is transferred from the second central processing value M8 to the first central processing unit 1, the operation is reversed to that described above. Then, the FIFO controller 11
Since it has a function to clear the contents of the IFO circuit 5a, for example, if the data transfer is interrupted due to an accident while transferring data from the first central processing unit 1 to the second central processing unit 8, the IFO circuit 5a can be cleared. 1 central processing unit 1 is FI
The FO circuit 5a is cleared and the next transfer is started normally.

〔Effect of the invention〕

As described above, according to the present invention, by making the data register a FIFO circuit several times larger, data can be transferred between central processing units at once, thereby improving the transfer speed. Since the transfer direction of the circuit is bidirectional, the scale of the bus interface circuit can be halved, and the FIFO controller can be configured with FTF.
The O circuit is equipped with a circuit-like function, so that even if a transfer is interrupted midway due to an accident, the next transfer can be started normally.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bus interface circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional bus interface circuit. In the figure, 1 is a first central processing unit, 2 is an address bus, 3 is a data bus, 4 is a control bus, and 5a
is the FIFO circuit, 6a is the FIFO status register,
7 is a port, 8 is a second central processing unit, 9 is a signal line A, 1011 signal line B, and 11 (fFrFO controller). In the figure, the same reference numerals indicate the same or equivalent parts. figure

Claims (1)

[Claims] A FIFO controller connected to the first central processing unit via an address bus, a FIFO status register, a FIFO circuit connected to the first central processing unit via a data bus, a FIFO controller, a FIF
O status register, first via control bus
FIFO status register connected to the central processing unit of , FIFO status register connected to the FIFO controller via signal line A, FIFO circuit connected to the FIFO controller via signal line B, FIFO via data bus circuit, a port connected to the FIFO status register, and the FIF via the address bus.
O controller, a port connected to the FIFO status register, a second central processing unit connected to the FIFO controller, a port connected to the FIFO status register via a control bus, an address bus, a data bus, a port via a control bus. A bus interface device comprising a processing device.