JPH04190445A - Bus interface device - Google Patents

Abstract

PURPOSE:To decrease the scale of a bus interface circuit while decreasing the transfer speed by using a FIFO circuit which has a data register with several bytes and setting batch transfer of data and its transfer direction between central processing units. CONSTITUTION:When data are transferred from a 1st central processing unit to a 2nd central processing unit 8, the 1st central processing unit 1 specifies the address of an FIFO controller 11 through an address bus 2, outputs a write signal from a control bus 4 to the FIFO controller 11, and indicates the transfer direction of the FIFO circuit to the FIFO circuit 5a through a signal line B10. When data are transferred from the 2nd central processing unit 8 to the 1st central processor 1, reverse operation is performed. Thus, the data register is used as the several times FIFO circuit, and the transfer is enabled in two directions; and the transfer speed is improved and the scale of the bus interface circuit is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a microcomputer having two central processing units,
The present invention relates to a p has interface device which is particularly designed to improve transfer speed in systems.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional pass-through-7 fuse circuit. In the figure, the first central processing unit 1 is an AF system bus 2, data bus 3, controller).
Via the roll bus 4, data register 5 and status 1.・Connected to DISCRO.

The data register 5 and the status register are connected via the atto L bus 2, the data bus 3, and the control bus 4.
Connected to port 1-7. On the other hand, the second central processing unit 8 is connected to the ports 1-7 via the system bus 2, data bus 3, control bus 4'e.

Next, the operation will be explained. First central processing unit 1
When transferring data from the control bus 4 to the second central processing unit 8, the first central processing unit 1 specifies the address of the status register row through the address bus 2, and outputs a read signal from the controller bus 4. , the state of the data bus 5 is checked by loading the contents of the stake register into the data bus 3. The status register is a register indicating the presence or absence of data in register 5. If there is no data in data register 5, status register 6 is used.
The beep indicating the presence or absence of data is cleared, and the first
The central processing unit 1 specifies the address of the data register 5 via the address bus 2, outputs a write signal to the control bus 4, outputs data to the data bus 3, and stores data of 1 byte) in the data register 5. Write. At this time, a signal is output from the data register 5 to the status register 6 via the signal line A9, and a bit indicating the presence or absence of the status register data is set. The first central processing unit 1 constantly monitors the status of the stake register, and the status register is sera).
Write data to disk 5 and stop writing.

The second central processing unit 8 also has a status register 6
When the status register is set, data is sent to the Attos bus 2, the address of the disk 5 is specified, a read signal is output to the control/roll bus 4, and the data register is read via the data bus 3. Take in 1 byte of data of 5. At this time, a signal is output from the data register 5 via the equal line A9, and the status register 6 is cleared. When transferring data from the second central processing unit 8 to the first central processing unit 1,
This is performed in the opposite manner to the above operation.

[Problem to be solved by the invention]

Since the conventional bus interface circuit 1 is configured as described above, data can only be transferred one byte at a time between central processing units, so there is a problem in that the transfer speed cannot be improved.

This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to obtain a bus interface circuit that can improve the data transfer speed between central processing units.

[Means to solve the problem]

The bus interface circuit according to the present invention is a FIFO controller having a data register of several bytes.
・Roller, FIFO status data register, 14”1j
E31E Processing "A fiE" is equipped with an address bus, a data bus, a control bus, and a port, and the central processing unit is connected to the FIFO circuit, F
IFO controller, FIFO status register,
FIFO controller, FIFO via ATIS bus
The data register 1 is connected to the FIFO status register via a control bus. FI
The FO circuit t circuit is connected to port 1 through the tabus.

The FIFO controller is connected to ports via an address bus and a control bus. The FIFO status register is connected to ports via an address bus, a data bus, and a control bus.

[Effect]

The bus innocuface device 1 according to the present invention uses a FIFO circuit with several data registers instead of a 1-byte data register, so data can be transferred in batches between central processing units. Furthermore, it is expected that the transfer speed will be improved, and since the transfer direction of the FIFO circuit can be set, the scale of the bus interface circuit can be halved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a bus interface circuit which is an embodiment of the present invention. In the figure, a first central processing unit N1 is connected to a FIFO controller 11 and a FIFO status register 6a via an address bus 2, and to a FIFO circuit 5a, a FIFO controller 11, a FIFO, z, and a take register via a data bus 3. to a,
FIFO: l via bus 4
I/O controller 11, FIFO status data 7 register 6a
is connected to. The FIFO circuit 5a is connected to port 7 via the data bus 3. FIFO Kono) Low-710! Atto bus 2, control bus 4
'i: Connected to ports 1 and 7 via. and,
FIFO status data-JSuf 6 a 1. ;t atto
L bus 2, Kono)・L7-no [Port j via bus 4
・Connect to 7). FIFO circuit 5a and FIFO controller 1-a --711! Yes: Connected via No. 1 BIo-Q. FIFO Co..., Troller 11 and F
IFO status data system clock alJ: via signal iA9 (
7 is connected. Then, the second central processing unit 8 connects the atto L bus 2 and the data bus 3 via the port 7.
, controller) and connect it to L bus 4).

Next, the operation will be explained. First central processing unit 1
When transferring data from the address bus 2 to the second central processing unit 8, the first central processing unit 1
Specify the address of the IFO controller 11 and send the write signal from controller 1 to roll bus 4 to the FIFO controller 11.
Output to. An equal sign indicating the transfer direction of the FIFO circuit is output from the FIFO: 172) roller 1 to the FIFO circuit 5a via the signal line BIO. In the present embodiment, the first central processing unit 1 via the first JA9 outputs the π number to the FiFO status data log a, and the flag indicating the presence or absence of data in the F[FO status data recorder 6a is output. ) 1- is Sera)・is done. 7. The first central processing unit 1 constantly monitors the status of the first FIFO circuit 6a by performing a FIFO sweep, and stops writing to the FIFO circuit 5R when the FIFO status is determined. 0, the second central processing unit 8 also uses the FIF
The status of the O status data system 6a is monitored, and the FI
FO status: , ; When the bit (indicating the presence or absence of data in block 6a) 1 is set, the FI
FO: 1:, j・Specify the address of roller 11, and press
Output the read out value to the low/L bus 4. The FIFO controller 1 which received this read signal outputs the read signal to the FIFO circuit 5a via the signal lines B and 0. Then, the data in the FIFO circuit 5a is
The data is taken into the central processing unit 8 of the computer. At this time, PIF
'0 controller 11 is FIFO via A9
Output No. 43 to the status disk 6a and clear the bit indicating the presence or absence of data in the FIFO status A. After that, the above operation will be repeated. Also, the second
When transferring data from the second central processing unit 8 to the first central processing unit 1, the operations described above should be reversed.

〔Effect of the invention〕

As described above, according to the present invention, by using a FIFO circuit several times as large as the data transfer circuit, data transfer between central processing units can be performed all at once with the -C1 transfer error in the left row. Furthermore, since the FIFO circuit has bidirectional transfer direction, the size of the bus interface circuit can be halved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bus interface circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional bus interface circuit. In the figure, 1 is a first central processing unit, 2 is an address bus, 3 is a data bus, 4 is a roll bus, and 5 is a roll bus.
a is a FIFO circuit, 6a is a FIFO status register, 7 is a port, 8 is a second central processing unit, 9 is a signal line A110 is a signal line B, and 11 is a FIFO controller. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Iwa Figure 2! 4-97°

Claims (1)

[Claims] A FIFO controller connected to the first central processing unit via an address bus, a FIFO status register, a FIFO circuit connected to the first central processing unit via a data bus, a FIFO controller, a FIFO
a FIFO status register connected to the first central processing unit via a control bus; a FIFO status register connected to the FIFO controller via signal line A;
FIFO circuit connected to IFO controller, FIFO circuit via data bus, port connected to FIFO status register, FIFO via address bus
a controller, a port connected to the FIFO status register, a second central processing unit connected to the FIFO controller, a port connected to the FIFO status register via a control bus, an address bus, a data bus, and a port via a control bus; A bus interface device comprising: