JPS61217847A - Detecting system for local memory error - Google Patents

Abstract

PURPOSE:To detect easily a local memory error by storing the same data into a pair of local memories and reading out the contents of both memories in a read mode to compare them with each other for detection of the discordance between them. CONSTITUTION:The read data delivered with e timing when the positive value of a local memory address counter 6 is given to the 1st and 2nd local memories 7 and 8 are stored in registers 9 and 10. A discordance detecting circuit 11 compares the data stored in the register 9 with the data delivered from the memory 8 with the timing when the negative value of the counter 6 is given to both memories 7 and 8. While a discordance detecting circuit 12 compares the data stored in the register 10 with the data delivered from the memory 7. Then a memory error detecting signal is delivered onto a signal line 15 when either one of both circuits 11 and 12 detects the discordance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a local memory error detection method in a source information processing device equipped with a peripheral control device that requires a local memory, and in particular to a method for detecting errors when reading data stored in the local memory. Regarding detection method.

(Prior art) Conventionally, this type of local memory error detection method has provided a parity pit storage area in the local memory, and when storing transferred data, parity pits are detected based on the stored data.
1-A configuration is adopted in which the data is generated and stored, and when read, the next data to be read and the parity bit are judged together to detect the presence or absence of a local memory error.

(Problems to be Solved by the Invention) As mentioned above, in the conventional local memory error detection method, since Sheller detection is performed using parity pits, an extra parity bit storage area is required in the local memory. This method has the disadvantage that nine parity bits must be generated corresponding to the stored data, which increases the data transfer cycle time.

An object of the present invention is to eliminate the above disadvantages by storing the same data in a pair of local memories, reading out the contents of the pair of local memories together at the time of reading, and detecting discrepancies by comparing the pair of read data. An object of the present invention is to provide a local memory error detection method configured to have a short data transfer cycle time.

(Ninth means to solve the problem) The local memory error detection method using fIAK is composed of a peripheral device, a central processing unit, a main memory device, and a peripheral control device. This is in a system that can be configured to match transfer speeds. In such systems, peripheral devices are capable of transferring data in 1-byte units, and peripheral control devices are connected to other devices via a bus and perform data transfer between them and the main memory. This is done in units of 2 bytes, and the data transfer rate with the peripheral device can be set several times faster than the data transfer rate with the main storage device.

In the above configuration, the peripheral control device includes a local memory address counter, first and second local memories,
first and second read registers;
This configuration includes a mismatch detection circuit and an OR gate.

The local memory address counter is capable of incrementing its value by one each time two bytes of data are output from the peripheral, and is intended to provide positive and negative addresses.

The first and second local memories are companions that store data on the bus corresponding to positive and negative addresses.

The first and second read registers correspond to the first and second local memories and store data read from the local memories, respectively.

The first mismatch detection circuit is for comparing the data stored in the second local memory and the data stored in the first read register.

The second mismatch detection circuit is the ninth one that compares the companion data stored in the first local memory with the data stored in the second read register.

The OR gate is for calculating the logical sum of the outputs of the first and second mismatch detection circuits and outputting a local memory error signal.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the local memory error detection method t' according to the present invention. In FIG. 1, 3 is a peripheral control device, 4 is a data bus, 5 is a peripheral device, 6 is a local memory address counter, 7, 8
are the first and second local memo IJ, respectively, 9.1
0 are the first and second read registers, respectively, 11.
12 are first and second mismatch detection circuits, respectively; 13
is OR+gate, 14 is flip-flop, 16°17
are the first and second address selectors, 18-
20 are first to third data selectors, 21.2
2 are first and second buffer gates, respectively.

In FIG. 1, the positive and negative outputs of the local memory address counter 6 are connected to a first local memory I77 via a first address selector 16, and similarly via a second address selector 17. It is connected to a second local memory 8. The first read data sent from the first local memory 7 to the signal line 23 is connected to one input of the first read register 9 and the second mismatch detection circuit 12. The second read data sent from the second local memory 8 to the signal line 24 is connected to one input of the second read register 10 and the first mismatch detection circuit 11.

The output of the first read register 9 is connected to the other input of the first mismatch detection circuit 11 and one input of the data selector 20, and is further connected to the 2-byte data bus via the first buffer gate 21. Connected to one side of 4.

The output of the second read register 10 is connected to the other input of the second mismatch detection circuit 12 and the other input of the third data selector 20, and further connected to the second buffer gate 2.
2 is connected to the other side of the 2-byte data bus 4. The output of the third data selector 20 is connected to the peripheral device 5.

The output of the first mismatch detection circuit 11 is connected to one input of the OR gate 13, and the output of the second mismatch detection circuit 11 is connected to the other input of the OR gate 13. OR
The output of the gate 13 is input to the flip-flop 14,
The local memory error detection signal output from the flip-flop 14 is sent onto the signal line 15. Peripheral device 5
The outputs are input to the first local memory 7 and the second local memory 8 via the first data selector 1B and the second data selector 19, respectively. 2
Each byte signal of the byte data bus is connected to a first data selector 18 and a second data selector 19.

FIG. 2 is a block diagram of a system in which a central processing unit 1, a main storage device 2, and a peripheral control device 3 whose block diagram is shown in FIG. 1 are connected to a 2-byte data bus 4.

Next, the entire operation of the apparatus shown in FIG. 1 will be explained with reference to FIGS. 3 to 7.

3 and 4 are output from the peripheral device 5 7'
(This is an explanatory diagram showing how 16 bytes of data from oo to OF are transferred to the main storage device 2. FIG. 3 shows how data is transferred from the peripheral device 5 to the first and second local memories 7.8. FIG. 4 is an explanatory diagram showing the relationship between local memory addresses and stored data when data is transferred. FIG. This is an explanatory diagram showing the relationship with comparison data. Fig. 5 is an explanatory diagram showing the relationship between the local memory address and stored data when data is transferred from the main storage device 2 to the peripheral control device. Figure 6 shows the first and second local memories 7.
8 is an explanatory diagram showing the relationship between a local memory address, read data, and comparison data when data is transferred from the peripheral device 8 to the peripheral device 5. FIG.

According to FIG. 3, the value of the local memory address counter 6 is incremented by 1 every time 2 bytes are output from the peripheral device 5.
The positive and negative outputs of are switched each time one byte is output from the peripheral device 5 by the first and second address selectors 16 and 17, and are applied to the first local memory 7 and the second local memory 8. I can see that it is being done. When the first local memory 7 is given a positive address, the second local memory 8 is given a negative address, and when the first local memory 7 is given a negative address, the second local memory 8 is given a negative address. The local memory 8 of No. 2 is given a positive address. The output signal from the peripheral device 5 is sent to the first and second data selectors 18.
, 19 to the first local memory 7 and second local memory 8, respectively, and are stored in correspondence with the given addresses.

FIG. 7 shows the first local memory 7 and the second local memory 7 after storage is completed.
FIG. 2 is an explanatory diagram showing the state of data storage with the local memory 8 of FIG.

Next, the first local memory 7 inside the peripheral control device 3
The operation of transferring data from the second local memory 8 to the main storage device 2 will be explained with reference to FIG.

When data is stored and in a steady state as shown in FIG. 7, and the local memory address counter 6 is updated from O to 7 as shown in FIG. The positive and negative outputs of the memory address counter 6 are alternately selected, and as shown in FIG. E... Axis-6, 9, 7, 8 in the order of the first
local memory 7 and a second local memory 8. At the timing when the positive value of the local memory address counter 6 is given to the first local memory 7 and the second local memory 8, the first read data output from the first local memory 7 is sent to the signal line 23. The second read data is stored in the first read register 9 via the signal line 2 and output from the second local memory 8.
4 and stored in the second read register 5o.

At the timing when the negative value of the local memory address counter 6 is given to the first local memory 7 and the second local memory 8, the first mismatch detection circuit 11 and the second local memory
The data stored in the first read register 9 and the second read data 2 sent from the second local memory 8 to the signal line 24 are compared with the mismatch detection circuit 12 of the second read register lO. The stored data and the first read data from the first local memory 7 to the signal line 23 are compared. Any mismatch detection circuit 11, 1
2, when a mismatch is detected, the OR gate 13t-
is stored in the flip-flop 14 via the signal line 15.
A local memory error detection signal is output upward.

The t data stored in the first read register 9 and the second read register 10 are output to the 2-byte data bus 4 via the first buffer gate 21 and the second buffer gate 22, respectively.

When the operation shown in FIG. 4 is executed after the operation shown in FIG. 3 is completed, there is no problem even if there is a difference between the data transfer speed of the peripheral device 5 and the data transfer speed of the 2-byte data bus 4.

As already explained, FIGS. 5 and 6 show that, contrary to the previously explained data transfer direction, data is output from the main memory 2 via the 2-byte data bus 4t in 8 transfer cycles. The following is an explanatory diagram showing how 16 bytes of data 7'qoo to oF are transferred to the peripheral device 5.

According to FIG. 5, the value of the local memory address counter 6 increases by 1 every time data is transferred from the main memory 2.
The positive and negative outputs of the local memory address counter 6 are switched by the first and second address selectors 16 and 17, respectively, while the data is being transferred from the main memory 2, and the first local memory seven days seven
It can be seen that the second local memory 8 is also provided. Furthermore, here, each time the output of the local memory address counter 6 given to the first local memory 7 and the second local memory 8 switches between positive and negative, the connection with the 2-byte data bus 4 is changed to the first local memory 7 and the second local memory 8. and second data selectors 18 and 19, which are connected to the first local memory 7 and the second local memory 8, so that the data of the pig buses facing each other are selected alternately.

Transfer data from the main storage device 2 is input to the first local memory 7 and the second local memory 8 via the first and second data selectors 18 and 19, respectively, and is stored at the given address. They are stored accordingly. The storage state of data in the first local memory 7 and the second local memory 8 after the storage is completed is the same as in the case of the cylinder shown in FIG. 7 and the operations in FIGS. 3 and 4. .

Next, the first local memory 7 inside the peripheral control device 3
The operation of transferring data from the second local memory 8 to the same side device 5 will be described with reference to FIG. When the data is stored as shown in Figure 7,
When the local memory address counter 6 is updated from O to 7 as shown in FIG. 6, the positive and negative outputs of the local memory address counter 6 are alternately selected by the first and second address selectors 16 and 17. As shown in Figure 6, o, F, 1. E.

. . . 6, 9, 7.8 are given to the first local memory I77 and the second local memory 8 in this order.

At the timing when the positive value of the local memory address counter 6 is given to the first local memory 7 and the second local memory 8, the first local memory 7 and the second local memory 8 output The first read data is stored in the first read register 9 via the signal line 23, and the second read data is stored in the second read register 0 via the signal line 24.

The mismatch detection operation is executed at the timing when the negative value of the local memory address counter 6 is given to the first local memory 7 and the second local memory 8, but the operation is the same as in the case of FIG. It is.

When the positive value of the local memory address counter 6 is given to the fifth local memory 7 and the second local memory 8, the output of the first read register 9 is given to the third local memory 7.
The data is output to the peripheral device 5 via the data selector 20, and at other times, the output of the second read register 10 is output in the same way.

The operation shown in FIG. 6 is executed after the operation shown in FIG.

(Effects of the Invention) As explained above, the present invention stores the same data in a pair of local memories, reads out the contents of the pair of local memories together at the time of reading, and compares the pair of read data to detect discrepancies. This detection has the effect that fi, ez-cal memory errors can be easily detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a local memory error detection method according to the present invention. FIG. 2 is a block diagram showing the fc system including the peripheral control device shown in FIG. 1. FIGS. 3 to 7 are explanatory diagrams showing the relationship between local addresses and stored data during data transfer. 1...Central processing unit WL 2...Main storage device 3.
... Peripheral control device 4 ... Data bus 5 ... Peripheral device 6 ... Local memory address counter 7.8 ... Local memory 9.10 ... Read register 11.12 ... Mismatch detection circuit 13 ...・・OR1 gate 14...Flip-flop 16.17...Address selector 18.19, 20-Success・Data selector 21.22・-
・Buffer gate 15.23, 24...Signal line

Claims (1)

[Claims] a peripheral device capable of transferring data in units of 1 byte, a central processing unit, a main storage device, and the peripheral device;
It is connected to the central processing unit and the main storage device via a bus, transfers data to and from the main storage device in units of 2 bytes, and controls the data transfer rate with the peripheral devices by controlling the data transfer rate with the peripheral device. A local memory error detection method in a system comprising a peripheral control device that can set the data transfer rate several times faster than the data transfer rate between the storage device and configured to match the data transfer byte unit and the data transfer rate. a local memory address counter capable of incrementing a value by 1 each time two bytes of data are output from the peripheral device; and first and second local memories for storing data on the bus in response to negative addresses;
first and second read registers for storing data respectively read from the local memories corresponding to the first and second local memories; a first mismatch detection circuit for comparing data stored in a first read register; and a first discrepancy detection circuit for comparing data stored in the first local memory and data stored in the second read register. a second mismatch detection circuit for detecting an error in the local memory; and an OR gate for calculating a logical sum of the outputs of the first and second mismatch detection circuits and outputting a local memory error signal. A local memory error detection method is characterized in that it is configured to be able to detect.