JPS60142425A - Scanning control system - Google Patents

Scanning control system

Info

Publication number
JPS60142425A
JPS60142425A JP25002583A JP25002583A JPS60142425A JP S60142425 A JPS60142425 A JP S60142425A JP 25002583 A JP25002583 A JP 25002583A JP 25002583 A JP25002583 A JP 25002583A JP S60142425 A JPS60142425 A JP S60142425A
Authority
JP
Japan
Prior art keywords
scan
signal
mode
gate
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25002583A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamazaki
弘 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25002583A priority Critical patent/JPS60142425A/en
Publication of JPS60142425A publication Critical patent/JPS60142425A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce time loss by discriminating whether data sent to the device side is a long mode or a short mode and processing the data on the device side in a scanning control system. CONSTITUTION:When data is sent from a service processor, a mode detecting circuit 12 decodes a scan address signal to identify whether the sent scan data are in the long mode or short mode on the divece side. In case of the long mode, a bit count 32 signal is received through an AND gate 6 and an FF0 is set by the output of the gate 6 to output a long scan end signal. In case of the short mode, a bit count 8 signal is received through an AND gate 7 and an FF10 is set by the output of the gate 7 to output a short scan end signal.

Description

【発明の詳細な説明】 α)発明の技術分野 本発明は情報処理システムにおけるサービスプロセッサ
と他の装置間のスキャン制御に関するものである。
Detailed Description of the Invention α) Technical Field of the Invention The present invention relates to scan control between a service processor and other devices in an information processing system.

(2) 従来技術と問題点 第1図はサービスプロセッサと他の装置の接続系統を示
す図で、1はサービスプロセッサ、2.〜2ユは装置、
3〜5は信号線である。
(2) Prior art and problems FIG. 1 is a diagram showing a connection system between a service processor and other devices. ~2U is the device,
3 to 5 are signal lines.

第1図において、サービスプロセッサ1は各装置21〜
2゜に対し、信号線3〜5を使用して情報をビットシリ
アルに転送し、これらの装置をスキャン制御している。
In FIG. 1, the service processor 1 includes each device 21 to
2 degrees, information is transferred bit-serial using signal lines 3 to 5, and these devices are scan-controlled.

信号線3は装置機番信号(並列信号)を、信号線4はス
キャンアドレス信号(並列信号)を、5はスキャンデー
タ信号(直列信号)をそれぞれ転送する。各装置2、〜
2ユでは信号線3上の機番信号が自機番と一致するとき
のみ信号線4.5を接続する。
The signal line 3 transfers a device number signal (parallel signal), the signal line 4 transfers a scan address signal (parallel signal), and the signal line 5 transfers a scan data signal (serial signal). Each device 2, ~
In the case of 2 units, the signal line 4.5 is connected only when the machine number signal on the signal line 3 matches the own machine number.

第2図はスキャン制御用レジスタを示す図で、夫々に異
なるスキャン・アドレスが付され、多数存在するレジス
タのうちの2つを示してあシ、矢印はシフト方向を示し
ておシ、INはスキャンイン側、OUTはスキャンアウ
ト側を、Dはデータ部を、人はアドレス部を、Cは制御
部を、Nは未使用部をそれぞれ表わしているもので、0
〜31の数字はビット位置である0従来、このようなス
キャン制御においては、装置側ではデータの長さに関係
なく1ワード(32ビツト)のスキャンが終了してから
処理を開始するので、制御部Cの情報が受信側のスキャ
ン制御レジスタ上で右方向にシフトされ、第2図のビッ
ト31の位置のデータがビット7の位置に到達したとき
、初めて装置側で制御内容が判別され処理が開始されて
いた。
Figure 2 is a diagram showing the scan control registers, each with a different scan address. Two of the many registers are indicated by ``A'', the arrow indicates the shift direction, and ``IN'' indicates the shift direction. OUT stands for the scan-in side, OUT stands for the scan-out side, D stands for the data section, LINE stands for the address section, C stands for the control section, and N stands for the unused section.
The number ~31 is the bit position 0 Conventionally, in this type of scan control, the device side starts processing after scanning one word (32 bits) regardless of the data length, so the control When the information in part C is shifted rightward on the scan control register on the receiving side and the data at bit 31 in Figure 2 reaches the bit 7 position, the control content is determined on the device side and processing is started for the first time. It had started.

従って制御部情報が転送されてから、これが装置側で解
読されるまでの時間的損失が大であると云う欠点があっ
た。
Therefore, there is a drawback that there is a large time loss from the time the control section information is transferred until it is decoded on the device side.

(3)発明の目的 本発明は上記従来の欠点に鑑み、スキャン制御に係る制
御部の情報を、早期に検出して処理全開始することによ
り時間的損失の減少を図ることの可能な方式を提供する
こと全目的としている。
(3) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method that can reduce time loss by detecting information in a control unit related to scan control early and starting full processing. The entire purpose is to provide

(4)発明の構成 そしてこの目的は本発明によれば特許請求の範囲に記載
のとおシ、サービスプロセッサによってビットシリアル
に複数バイトを単位として制御される装置において、転
送される情報の有効バイト数が何バイトであるがをサー
ビスプロセッサからのスキャンアドレス信れるビットに
よそ情報に基いて処理を開始することを特徴とするスキ
ャン制御方式により達成される。
(4) Structure and object of the invention According to the present invention, the effective number of bytes of information to be transferred in a device controlled bit-serially in units of multiple bytes by a service processor is as described in the claims. This is achieved by a scan control method characterized in that processing is started based on information about the number of bytes in the scan address from the service processor.

(5) 発明の実施例 第3図は本発明の1実施例に用いる識別回路ノ回路図で
あって、サービスプロセッサカらのスキャン制御データ
の制御部からメモリライト信号全検出する回路を示すも
のであ枳6〜8はアンドゲート、9〜11はフリップフ
ロップ、12はモード検出回路を表わしている0 第3図において、サービスプロセッサよシ、データが送
られる場合は、装置側で、スキャンアドレス信号(第1
図の信号線4で送られるアドレス信号)全モード検出回
路12でデコードし、送られて来るスキャンデータがロ
ングモード(32ビツト)であるかショートモード(8
ビツト)であるかを識別して、それぞれに設けたゲート
ヲ制御している。例えば第2図に示した上側のレジスタ
にデータ部(D)、アドレス部(A)のデータが送られ
る場合は、該レジスタを指示するスキャンアドレスより
ロングモード信号と検出され、第3図のアンドゲート6
を生かしてビットカウント32信号を受けた該ゲート6
の出力にょクツリップフロップ9をセットしてロングス
キャンエンド信号全出力する。また第2図に示した下側
のレジスタに制御部(C)k受信する際には、そのスキ
ャンアドレスよりショートモードと検出され、第3図の
アンドゲート7を生かしてビットカウント8信号を受け
た該ゲート7の出力によりフリップフロップ10をセッ
トして、ショートスキャンエンド信号孕出力する。該シ
ョートスキャンエンド信号はアンドゲート8に入力され
、該アンドゲート8はスキャンアドレスとビット31(
メモリライトを表わすビット)の条件でフリップフロッ
プ11をセットして、メモリライト信号を出力する。
(5) Embodiment of the Invention FIG. 3 is a circuit diagram of an identification circuit used in an embodiment of the present invention, and shows a circuit for detecting all memory write signals from a control section for scan control data from a service processor. 6 to 8 are AND gates, 9 to 11 are flip-flops, and 12 is a mode detection circuit.0 In Figure 3, when data is sent from the service processor, the scan address is Signal (1st
The address signal sent via signal line 4 in the figure) is decoded by the all mode detection circuit 12 to determine whether the scan data being sent is long mode (32 bits) or short mode (8 bits).
It identifies whether it is a bit or not and controls the gate provided for each. For example, when data in the data field (D) and address field (A) are sent to the upper register shown in Figure 2, a long mode signal is detected from the scan address that specifies the register, and the AND gate 6
The gate 6 receives the bit count 32 signal by making use of the
The output flip-flop 9 is set to output all long scan end signals. Furthermore, when receiving the control unit (C)k to the lower register shown in Figure 2, the short mode is detected from the scan address, and the bit count 8 signal is received using the AND gate 7 in Figure 3. The flip-flop 10 is set by the output of the gate 7, and a short scan end signal is output. The short scan end signal is input to the AND gate 8, and the AND gate 8 inputs the scan address and bit 31 (
The flip-flop 11 is set under the conditions of the bit representing memory write, and a memory write signal is output.

(6)発明の効果 本発明の方式によれば、サービスプロセッサによる各装
置のスキャン制御に際し、装置側で、スキャンアドレス
情報に基いて、送られて来るデータがロングモードであ
るかショートモードであるか全識別して処理するので、
時間的損失が少なく、効率的な制御が行える利点がある
(6) Effects of the Invention According to the method of the present invention, when the service processor scans each device, the device side determines whether the data sent is in long mode or short mode based on the scan address information. Since it identifies and processes all
This has the advantage of less time loss and efficient control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はサービスプロセッサと他の装置の接続系統を示
す図、第2図はスキャン制御用レジスタ金示す図、第3
図は本発明の1実施例に用いる識別回路の回路図である
Figure 1 shows the connection system between the service processor and other devices, Figure 2 shows the scan control register, and Figure 3 shows the connection system between the service processor and other devices.
The figure is a circuit diagram of an identification circuit used in one embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] サービスプロセッサによってビットシリアルに複数バイ
トを単位として制御される装置において、転送される情
報の有効バイト数が何バイトであるかをサービスプロセ
ッサからのスキャンアドレス信号によって識別して、当
該するバイト数の情報を受信後直ちに該情報あるいは該
情報に含まれるビットによる情報に基いて処理全開始す
ることを特徴とするスキャン制御方式。
In a device that is controlled by a service processor bit-serially in units of multiple bytes, the number of effective bytes of information to be transferred is identified by a scan address signal from the service processor, and information on the number of bytes is identified. A scan control method characterized in that immediately after receiving the information, all processing is started based on the information or the information based on the bits included in the information.
JP25002583A 1983-12-28 1983-12-28 Scanning control system Pending JPS60142425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25002583A JPS60142425A (en) 1983-12-28 1983-12-28 Scanning control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25002583A JPS60142425A (en) 1983-12-28 1983-12-28 Scanning control system

Publications (1)

Publication Number Publication Date
JPS60142425A true JPS60142425A (en) 1985-07-27

Family

ID=17201717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25002583A Pending JPS60142425A (en) 1983-12-28 1983-12-28 Scanning control system

Country Status (1)

Country Link
JP (1) JPS60142425A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63109531A (en) * 1986-10-28 1988-05-14 Nec Corp Card recognition system
JPS63300347A (en) * 1987-05-30 1988-12-07 Fujitsu Ten Ltd Data transfer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63109531A (en) * 1986-10-28 1988-05-14 Nec Corp Card recognition system
JPS63300347A (en) * 1987-05-30 1988-12-07 Fujitsu Ten Ltd Data transfer system

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