JPH04146631A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH04146631A
JPH04146631A JP2271044A JP27104490A JPH04146631A JP H04146631 A JPH04146631 A JP H04146631A JP 2271044 A JP2271044 A JP 2271044A JP 27104490 A JP27104490 A JP 27104490A JP H04146631 A JPH04146631 A JP H04146631A
Authority
JP
Japan
Prior art keywords
electrode
integrated circuit
hybrid integrated
conductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2271044A
Other languages
English (en)
Inventor
Kenichi Ono
大野　兼一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2271044A priority Critical patent/JPH04146631A/ja
Publication of JPH04146631A publication Critical patent/JPH04146631A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路の構造に関し、特に搭載する部品
の接続方法に関する。
〔従来の技術〕
従来より混成集積回路は半導体集積回路、絶縁性基板上
に一体的に形成されるか搭載される抵抗或いはコンデン
サを別途の部品として単独で或いは複数組合せて絶縁性
基板上で相互に接続することにより作られており、絶縁
性基板についてはその表裏を有効に利用することにより
混成集積回路の実装密度を上げる工夫をして来ているが
、その場合でも搭載する面が両面となる為に他面に部品
が既に搭載されている場合の搭載方法或いは部品端子の
接続方法は制約を受ける。
〔発明が解決しようとする課題〕
上述した従来の構造では混成集積回路を構成するだめに
半導体部品と抵抗コンデンサ等の受動部分を別個の部分
として組合せていたので、絶縁性基板の表裏を使うだけ
では全体の面積が大きくなるという欠点があった。
第３図は従来から実施して来た混成集積回路の構造を示
す断面図である。第３図に於いて１は電気的に絶縁性を
示すガラスエポキシ系等の有機材料或いはアルミナセラ
ミック等の無機材料からなる基板であり、その基板１の
上に抵抗体３．配線用の導体２が形成されている。Ｓｉ
の単結晶等をペースとした半導体集積回路（以下ＩＣ）
４は基板１の上に設けられたＩＣｄ用のマウントランド
５の上に塗布された接着剤６等により固定されている。
又ＩＣ４は周囲の電子部品例えば抵抗２と電気的に接続
する為にボンディンダ用の金等の金属細線７により接続
が為さ九ている。
〔課題を解決するための手段〕
本発明による混成集積回路はシリコンチップ表裏にそれ
ぞれ半導体集積回路及び受動部品を備えた電子部品を有
している。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明の一実施例を示す断面図である。
１は電気的に絶縁性を示すガラスエポキシ系等の有機材
料或いはアルミナセラミック等の無機材料からなる基板
を示し、その上に接続及び配線用の導体２が形成されて
いる。１１は基板１の上に搭載された電子部品を示す。
電子部品１１の表面側にはトランジスタ等の能動部分２
１が形成され絶縁層２２．２３により保護されると共に
絶縁層２２の開口部を通して導体層２４により電子部品
１１内部での配線が為されると共に外部へ接続する為の
電極２５が形成される。電子部品１１の裏面側には絶縁
層３１の上に抵抗体層３２さらに導体層３３が形成され
ている。
電子部品１１は電極２５を介して電極２とはんだ付は或
いは熱圧着等の方法により接続された後、抵抗体層３２
の上に形成された導体層３３と電極２′が金等の金属細
線３４により接続される。
第２図は本発明の実施例２の断面図である。本例では予
め配列されて保護板３５によりその間隔、向きが一定に
保たれそれぞれの両端が電極２′３３に平行になるよう
に曲げられさらに予備的にはんだ或いは金等の接続用電
極３７が付着されたリード列３６をはんだリフロー又は
熱圧着等により、電極２’、３３に接続した状態を示し
ている。
この場合は電子部品１４表面側の接続が一括で可能とな
るばかりではなく、反対側の接続についても一括又は電
子部品１１の各辺の各リード列毎に一括で接続できる利
点がある。
〔発明の効果〕
以上説明したように本発明の混成集積回路は搭載する電
子部品の両面に能動部分、受動部分を持つことにより、
混成集積回路の使用部品数を減らすと共にその面積を小
さくすることが可能であるばかりではなく搭載部品の接
続に掛る作業時間を短縮できる効果がある。
尚実施例では電子部品裏面に形成する受動部分の例に抵
抗のみを示したがコンデンサ或いはコイルとなるべき部
分を作ることが可能なことは熱論である。
【図面の簡単な説明】
第１図および第２図はそれぞれ本発明による混成集積回
路の実施例を示す断面図であり、第３図は従来より実施
されている混成集積回路の構造を示す断面図である。 ｌ・・・・・・基板、２，２′・・・・・・導体、３・
・・・・・抵抗体、４・・・・・・ＩＣｌ３・・・・・
・マウントランド、６・・・・・・接着剤、７・・・・
・・金細線、１１・・・・・・電子部品、２１・・・・
・・能動部分、２２．２３・・・・・・絶縁層、２４・
・・・・・導体層、２５・・・・・・電極、３１・・・
・・・絶縁層、３２・・・・・・抵抗体層、３３・・・
・・・導体層、３４・・・・・・金細線、３５・・・・
・保持板、３６・・・・・・リード列、３７・・・・・
・接続用電極。 代理人　弁理士　　内　原　　　晋 卒 ツ アー、、ｐ ／ｌ−雷）卯シ ２／−］障却斧 ２５−１電秒 ３１−・−詰妹層 ３４−　　釦り、ｔｄＬ ２．２’−導林 ２２．２３ 虻絡暫 一抵瓶停層 導体層 矩ｇｋ 弗 基板 電）降乙 伯勤舒全 ４Ｅ′ｐＰ 肴鴬所 ２．２′ ２２、：Ｂ わ 此舛ル 醪讃希 翠恰僧　３３−一−ｇ１所 ＃ｖｆ板　　　３６−一一り−１−列 吻朗攬極

Claims (1)

  1. 【特許請求の範囲】 １、表裏両面に能動部分および受動部分を有する電子部
    品の、絶縁性基板上の導体部分にあい対する面の電極と
    、絶縁性基板上の導体部分とを接続した後、該電子部分
    の他の面にある電極と絶縁性基板上の導体部分とを接続
    したことを特徴とする混成集積回路。 ２、あい対する電極どうしの接続をバンプ形式の電極に
    よるハンダリフロー又は熱圧着接続により行ない、電子
    部品の他の面側の接続を金又はアルミニュウム等の細線
    によるボンディングにより接続したことを特徴とする特
    許請求の範囲第１項記載の混成集積回路。 ３、電子部品の他の面側の接続を予め形成され、間隔・
    方向を一定に保持されたリード列を介して行なうことを
    特徴とする特許請求の範囲第２項記載の混成集積回路。
JP2271044A 1990-10-09 1990-10-09 混成集積回路 Pending JPH04146631A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2271044A JPH04146631A (ja) 1990-10-09 1990-10-09 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2271044A JPH04146631A (ja) 1990-10-09 1990-10-09 混成集積回路

Publications (1)

Publication Number Publication Date
JPH04146631A true JPH04146631A (ja) 1992-05-20

Family

ID=17494623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2271044A Pending JPH04146631A (ja) 1990-10-09 1990-10-09 混成集積回路

Country Status (1)

Country Link
JP (1) JPH04146631A (ja)

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