JPH0373139B2 - - Google Patents

Info

Publication number
JPH0373139B2
JPH0373139B2 JP59147702A JP14770284A JPH0373139B2 JP H0373139 B2 JPH0373139 B2 JP H0373139B2 JP 59147702 A JP59147702 A JP 59147702A JP 14770284 A JP14770284 A JP 14770284A JP H0373139 B2 JPH0373139 B2 JP H0373139B2
Authority
JP
Japan
Prior art keywords
layer
region
silicon
substrate
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59147702A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6088468A (ja
Inventor
Daaru Marauiya Shaashi
Ramasamiengaa Suriniuasan Gurumakonda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6088468A publication Critical patent/JPS6088468A/ja
Publication of JPH0373139B2 publication Critical patent/JPH0373139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
JP59147702A 1983-10-13 1984-07-18 半導体集積装置の製造方法 Granted JPS6088468A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54162683A 1983-10-13 1983-10-13
US541626 1983-10-13

Publications (2)

Publication Number Publication Date
JPS6088468A JPS6088468A (ja) 1985-05-18
JPH0373139B2 true JPH0373139B2 (enExample) 1991-11-20

Family

ID=24160384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59147702A Granted JPS6088468A (ja) 1983-10-13 1984-07-18 半導体集積装置の製造方法

Country Status (3)

Country Link
EP (1) EP0137195B1 (enExample)
JP (1) JPS6088468A (enExample)
DE (1) DE3468782D1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0641022B1 (en) * 1993-08-31 2006-05-17 STMicroelectronics, Inc. Isolation structure and method for making same
CN110061066B (zh) * 2019-04-30 2024-02-09 苏州固锝电子股份有限公司 一种浅沟槽的电极同侧二极管芯片的制造工艺
CN118398485B (zh) * 2024-06-27 2024-09-13 合肥晶合集成电路股份有限公司 半导体器件的制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372063A (en) * 1964-12-22 1968-03-05 Hitachi Ltd Method for manufacturing at least one electrically isolated region of a semiconductive material
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
US4141765A (en) * 1975-02-17 1979-02-27 Siemens Aktiengesellschaft Process for the production of extremely flat silicon troughs by selective etching with subsequent rate controlled epitaxial refill
US3972754A (en) * 1975-05-30 1976-08-03 Ibm Corporation Method for forming dielectric isolation in integrated circuits
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS58154256A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 半導体装置
JPS58220444A (ja) * 1982-06-16 1983-12-22 Toshiba Corp 半導体装置の製造方法
KR880000975B1 (ko) * 1982-08-24 1988-06-07 니혼덴싱뎅와 가부시끼가이샤 반도체 장치의 기판구조 및 그 제조방법

Also Published As

Publication number Publication date
DE3468782D1 (en) 1988-02-18
EP0137195B1 (en) 1988-01-13
EP0137195A1 (en) 1985-04-17
JPS6088468A (ja) 1985-05-18

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