JPH0342498B2 - - Google Patents

Info

Publication number
JPH0342498B2
JPH0342498B2 JP59190959A JP19095984A JPH0342498B2 JP H0342498 B2 JPH0342498 B2 JP H0342498B2 JP 59190959 A JP59190959 A JP 59190959A JP 19095984 A JP19095984 A JP 19095984A JP H0342498 B2 JPH0342498 B2 JP H0342498B2
Authority
JP
Japan
Prior art keywords
dam
wiring layer
layer
wiring
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59190959A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61179545A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP59190959A priority Critical patent/JPS61179545A/ja
Publication of JPS61179545A publication Critical patent/JPS61179545A/ja
Publication of JPH0342498B2 publication Critical patent/JPH0342498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP59190959A 1984-09-12 1984-09-12 半導体装置用配線基板の製造方法 Granted JPS61179545A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59190959A JPS61179545A (ja) 1984-09-12 1984-09-12 半導体装置用配線基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59190959A JPS61179545A (ja) 1984-09-12 1984-09-12 半導体装置用配線基板の製造方法

Publications (2)

Publication Number Publication Date
JPS61179545A JPS61179545A (ja) 1986-08-12
JPH0342498B2 true JPH0342498B2 (enExample) 1991-06-27

Family

ID=16266519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59190959A Granted JPS61179545A (ja) 1984-09-12 1984-09-12 半導体装置用配線基板の製造方法

Country Status (1)

Country Link
JP (1) JPS61179545A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691128B2 (ja) * 1988-05-10 1994-11-14 日本電気株式会社 電子機器装置

Also Published As

Publication number Publication date
JPS61179545A (ja) 1986-08-12

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