JPH0332832B2 - - Google Patents

Info

Publication number
JPH0332832B2
JPH0332832B2 JP58066890A JP6689083A JPH0332832B2 JP H0332832 B2 JPH0332832 B2 JP H0332832B2 JP 58066890 A JP58066890 A JP 58066890A JP 6689083 A JP6689083 A JP 6689083A JP H0332832 B2 JPH0332832 B2 JP H0332832B2
Authority
JP
Japan
Prior art keywords
substrate
card
board
module
cards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58066890A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59193596A (ja
Inventor
Masao Muramatsu
Yoshihiko Nakahara
Toshio Haga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyodo Printing Co Ltd
Original Assignee
Kyodo Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyodo Printing Co Ltd filed Critical Kyodo Printing Co Ltd
Priority to JP58066890A priority Critical patent/JPS59193596A/ja
Publication of JPS59193596A publication Critical patent/JPS59193596A/ja
Publication of JPH0332832B2 publication Critical patent/JPH0332832B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Credit Cards Or The Like (AREA)
JP58066890A 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル Granted JPS59193596A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58066890A JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066890A JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Publications (2)

Publication Number Publication Date
JPS59193596A JPS59193596A (ja) 1984-11-02
JPH0332832B2 true JPH0332832B2 (cs) 1991-05-14

Family

ID=13328953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58066890A Granted JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Country Status (1)

Country Link
JP (1) JPS59193596A (cs)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133489A (ja) * 1984-12-03 1986-06-20 Mitsubishi Plastics Ind Ltd メモリ−カ−ド
JPH0752462B2 (ja) * 1985-03-04 1995-06-05 カシオ計算機株式会社 カ−ド状電子機器
JPH0524551Y2 (cs) * 1985-07-26 1993-06-22
JPS6265270U (cs) * 1985-10-15 1987-04-23
JPS6265275U (cs) * 1985-10-16 1987-04-23
JPH0450145Y2 (cs) * 1985-10-16 1992-11-26
JPS62124996A (ja) * 1985-11-25 1987-06-06 日本電気株式会社 Ｉｃカ−ド
JPS62109973U (cs) * 1985-12-27 1987-07-13
JP2510520B2 (ja) * 1986-06-11 1996-06-26 大日本印刷株式会社 Ｉｃカ−ドおよびｉｃカ−ド用ｉｃモジユ−ル
JP2524585B2 (ja) * 1986-12-15 1996-08-14 日立マクセル株式会社 Ｉｃカ−ドとその作製方法
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
JPH08276688A (ja) * 1995-04-21 1996-10-22 Mahr Reonard Manag Co 回路チップ担持装置及びその製造方法
JP2719315B2 (ja) * 1995-04-21 1998-02-25 マー レオナード マネージメント カンパニー カード装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5231672A (en) * 1975-09-05 1977-03-10 Hitachi Ltd Ceramic package
FR2404990A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Substrat d'interconnexion de composants electroniques a circuits integres, muni d'un dispositif de reparation
FR2404992A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Circuits electriques integres proteges, substrats d'interconnexion proteges comportant de tels circuits et procede d'obtention desdits circuits et substrats
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
FR2439438A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Ruban porteur de dispositifs de traitement de signaux electriques, son procede de fabrication et application de ce ruban a un element de traitement de signaux
JPS55105398A (en) * 1979-02-08 1980-08-12 Cho Lsi Gijutsu Kenkyu Kumiai High packing density multilayer circuit board

Also Published As

Publication number Publication date
JPS59193596A (ja) 1984-11-02

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