JPS59193596A - Ｉｃカ−ド用ｉｃモジユ−ル - Google Patents

Ｉｃカ−ド用ｉｃモジユ−ル

Info

Publication number
JPS59193596A
JPS59193596A JP58066890A JP6689083A JPS59193596A JP S59193596 A JPS59193596 A JP S59193596A JP 58066890 A JP58066890 A JP 58066890A JP 6689083 A JP6689083 A JP 6689083A JP S59193596 A JPS59193596 A JP S59193596A
Authority
JP
Japan
Prior art keywords
module
card
substrate
chip
cards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58066890A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0332832B2 (cs
Inventor
Masao Muramatsu
村松　正男
Yoshihiko Nakahara
中原　義彦
Toshio Haga
芳賀　敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyodo Printing Co Ltd
Original Assignee
Kyodo Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyodo Printing Co Ltd filed Critical Kyodo Printing Co Ltd
Priority to JP58066890A priority Critical patent/JPS59193596A/ja
Publication of JPS59193596A publication Critical patent/JPS59193596A/ja
Publication of JPH0332832B2 publication Critical patent/JPH0332832B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Credit Cards Or The Like (AREA)
JP58066890A 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル Granted JPS59193596A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58066890A JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066890A JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Publications (2)

Publication Number Publication Date
JPS59193596A true JPS59193596A (ja) 1984-11-02
JPH0332832B2 JPH0332832B2 (cs) 1991-05-14

Family

ID=13328953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58066890A Granted JPS59193596A (ja) 1983-04-18 1983-04-18 Ｉｃカ−ド用ｉｃモジユ−ル

Country Status (1)

Country Link
JP (1) JPS59193596A (cs)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133489A (ja) * 1984-12-03 1986-06-20 Mitsubishi Plastics Ind Ltd メモリ−カ−ド
JPS61201389A (ja) * 1985-03-04 1986-09-06 Casio Comput Co Ltd カ−ド状電子機器
JPS6222871U (cs) * 1985-07-26 1987-02-12
JPS6265275U (cs) * 1985-10-16 1987-04-23
JPS6265270U (cs) * 1985-10-15 1987-04-23
JPS6265276U (cs) * 1985-10-16 1987-04-23
JPS62124996A (ja) * 1985-11-25 1987-06-06 日本電気株式会社 Ｉｃカ−ド
JPS62109973U (cs) * 1985-12-27 1987-07-13
JPS62290590A (ja) * 1986-06-11 1987-12-17 大日本印刷株式会社 Ｉｃカ−ドおよびｉｃカ−ド用ｉｃモジユ−ル
JPS63149192A (ja) * 1986-12-15 1988-06-21 日立マクセル株式会社 Ｉｃカ−ドとその作製方法
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
JPH08276688A (ja) * 1995-04-21 1996-10-22 Mahr Reonard Manag Co 回路チップ担持装置及びその製造方法
JPH08276689A (ja) * 1995-04-21 1996-10-22 Mahr Reonard Manag Co カード装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5231672A (en) * 1975-09-05 1977-03-10 Hitachi Ltd Ceramic package
JPS5460566A (en) * 1977-10-03 1979-05-16 Cii Chip forming ic and method of fabricating same
JPS5461669A (en) * 1977-10-03 1979-05-18 Cii Substrate of mutually connecting integrated circuit element provided with variable structure
JPS5556639A (en) * 1978-10-19 1980-04-25 Cii Strip for carrying device for processing electric signal and method of manufacturing same
JPS5556647A (en) * 1978-10-19 1980-04-25 Cii Honeywell Bull Flat package for at least one integrated circuit device
JPS55105398A (en) * 1979-02-08 1980-08-12 Cho Lsi Gijutsu Kenkyu Kumiai High packing density multilayer circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5231672A (en) * 1975-09-05 1977-03-10 Hitachi Ltd Ceramic package
JPS5460566A (en) * 1977-10-03 1979-05-16 Cii Chip forming ic and method of fabricating same
JPS5461669A (en) * 1977-10-03 1979-05-18 Cii Substrate of mutually connecting integrated circuit element provided with variable structure
JPS5556639A (en) * 1978-10-19 1980-04-25 Cii Strip for carrying device for processing electric signal and method of manufacturing same
JPS5556647A (en) * 1978-10-19 1980-04-25 Cii Honeywell Bull Flat package for at least one integrated circuit device
JPS55105398A (en) * 1979-02-08 1980-08-12 Cho Lsi Gijutsu Kenkyu Kumiai High packing density multilayer circuit board

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133489A (ja) * 1984-12-03 1986-06-20 Mitsubishi Plastics Ind Ltd メモリ−カ−ド
JPS61201389A (ja) * 1985-03-04 1986-09-06 Casio Comput Co Ltd カ−ド状電子機器
JPS6222871U (cs) * 1985-07-26 1987-02-12
JPS6265270U (cs) * 1985-10-15 1987-04-23
JPS6265275U (cs) * 1985-10-16 1987-04-23
JPS6265276U (cs) * 1985-10-16 1987-04-23
JPS62124996A (ja) * 1985-11-25 1987-06-06 日本電気株式会社 Ｉｃカ−ド
JPS62109973U (cs) * 1985-12-27 1987-07-13
JPS62290590A (ja) * 1986-06-11 1987-12-17 大日本印刷株式会社 Ｉｃカ−ドおよびｉｃカ−ド用ｉｃモジユ−ル
JPS63149192A (ja) * 1986-12-15 1988-06-21 日立マクセル株式会社 Ｉｃカ−ドとその作製方法
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
JPH08276688A (ja) * 1995-04-21 1996-10-22 Mahr Reonard Manag Co 回路チップ担持装置及びその製造方法
JPH08276689A (ja) * 1995-04-21 1996-10-22 Mahr Reonard Manag Co カード装置

Also Published As

Publication number Publication date
JPH0332832B2 (cs) 1991-05-14

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