JPH0332447U - - Google Patents
Info
- Publication number
- JPH0332447U JPH0332447U JP9210589U JP9210589U JPH0332447U JP H0332447 U JPH0332447 U JP H0332447U JP 9210589 U JP9210589 U JP 9210589U JP 9210589 U JP9210589 U JP 9210589U JP H0332447 U JPH0332447 U JP H0332447U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- chip
- led
- connection
- led chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
第１図は、本考案の第１実施例を説明する概略
説明図、第２図は、本考案の第２実施例を説明す
る概略説明図、第３図は、本考案の第３実施例を
説明する概略説明図、第４図は、従来のＬＥＤチ
ツプの実装構造を示す概略説明図である。
１，１１，２１……ＬＥＤチツプの実装構造、
２，１２，２２……プリント配線基板、３，１３
，２３……ＬＥＤチツプ、４，１４，２４……ド
ライバＩＣチツプ、５ａ……ＬＥＤ用パターン、
５ｂ……接続用パターン、５ｃ，１５，２５……
ＩＣ用パターン、６，１６，２６……光通過孔、
７……発光面、８ａ，８ｂ，１８，２８……ＬＥ
Ｄ電極、９……半田バンプ、１０ａ，１０ｂ，２
０ｂ，３０ｂ……下部電極、２０ａ，３０ａ……
接続用電極、３１……貫通孔。
FIG. 1 is a schematic explanatory diagram for explaining the first embodiment of the present invention, FIG. 2 is a schematic explanatory diagram for explaining the second embodiment of the present invention, and FIG. 3 is a schematic explanatory diagram for explaining the second embodiment of the present invention. FIG. 4 is a schematic explanatory diagram showing the mounting structure of a conventional LED chip. 1, 11, 21... LED chip mounting structure,
2, 12, 22...Printed wiring board, 3, 13
, 23... LED chip, 4, 14, 24... Driver IC chip, 5a... LED pattern,
5b... Connection pattern, 5c, 15, 25...
IC pattern, 6, 16, 26...light passing hole,
7...Light emitting surface, 8a, 8b, 18, 28...LE
D electrode, 9...Solder bump, 10a, 10b, 2
0b, 30b... lower electrode, 20a, 30a...
Connection electrode, 31...through hole.
Claims (1)
気的に接続してプリント配線基板に実装するＬＥ
Ｄチツプの実装構造において、 前記プリント配線基板には、ＬＥＤ用パターン
と接続用パターンとＩＣ用パターンとが夫々形成
されるとともにＬＥＤ用パターンと接続用パター
ンとの間に光通過孔を設け、 前記ドライバＩＣチツプでは、その下面に形成
した下部電極が半田バンプを介してＩＣ用パター
ンと接続用パターンとに接続され、 前記ＬＥＤチツプには、その下面に設けた発光
面が光通過孔に対向して配置されるとともに下面
に形成したＬＥＤ電極が半田バンプを介して接続
用パターンとＬＥＤ用パターンとに接続されたこ
とを特徴とするＬＥＤチツプの実装構造。 (2) 前記プリント配線基板には、ＩＣ用パター
ンが形成されるとともにＩＣ用パターンの外側一
方に光通過孔を設け、 前記ドライバＩＣチツプでは、その下面に形成
した下部電極が半田バンプを介して前記ＩＣ用パ
ターンに接続されて、かつ上面に接続用電極が形
成され、 前記ＬＥＤチツプには、その下面の一方側に設
けた発光面が前記光通過孔に対向して配置される
とともに下面の他方側に形成したＬＥＤ電極が半
田バンプを介して前記接続用電極に接続されたこ
とを特徴とする請求項１記載のＬＥＤチツプの実
装構造。 (3) 前記プリント配線基板には、複数のＩＣ用
パターンが形成されるとともに各ＩＣ用パターン
の間に光通過孔を設け、 前記ドライバＩＣチツプでは、その中央に設け
た貫通孔が前記光通過孔に対向して配置されると
ともに下面両外側に形成した下部電極が半田バン
プを介して前記ＩＣ用パターンに接続されてかつ
上面両外側に接続用電極が形成され、 前記ＬＥＤチツプには、その下面中央に設けた
発光面が前記貫通孔に対向して配置されるととも
に下面両外側に形成したＬＥＤ電極が半田バンプ
を介して前記接続用電極に接続されたことを特徴
とする請求項１記載のＬＥＤチツプの実装構造。[Scope of claim for utility model registration] (1) LE that electrically connects a driver IC chip and an LED chip and mounts them on a printed wiring board
In the D-chip mounting structure, an LED pattern, a connection pattern, and an IC pattern are formed on the printed wiring board, and a light passage hole is provided between the LED pattern and the connection pattern, In the driver IC chip, a lower electrode formed on the lower surface is connected to the IC pattern and the connection pattern via solder bumps, and the LED chip has a light emitting surface provided on the lower surface facing the light passage hole. 1. A mounting structure for an LED chip, characterized in that an LED electrode formed on the lower surface of the chip is connected to a connection pattern and an LED pattern via a solder bump. (2) An IC pattern is formed on the printed wiring board, and a light passage hole is provided on one side of the outside of the IC pattern, and the lower electrode formed on the lower surface of the driver IC chip is connected to the driver IC chip through a solder bump. A connection electrode is connected to the IC pattern and formed on the upper surface, and the LED chip has a light emitting surface provided on one side of the lower surface facing the light passage hole, and a light emitting surface provided on one side of the lower surface of the LED chip. 2. The LED chip mounting structure according to claim 1, wherein the LED electrode formed on the other side is connected to the connection electrode via a solder bump. (3) A plurality of IC patterns are formed on the printed wiring board, and a light passage hole is provided between each IC pattern, and in the driver IC chip, a through hole provided in the center is formed to allow the light passage. A lower electrode disposed facing the hole and formed on both outer sides of the lower surface is connected to the IC pattern via a solder bump, and connection electrodes are formed on both outer sides of the upper surface, and the LED chip has the following: 2. A light emitting surface provided at the center of the lower surface is disposed opposite to the through hole, and LED electrodes formed on both outer sides of the lower surface are connected to the connection electrode via solder bumps. Mounting structure of LED chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9210589U JPH0332447U (en) | 1989-08-04 | 1989-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9210589U JPH0332447U (en) | 1989-08-04 | 1989-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332447U true JPH0332447U (en) | 1991-03-29 |
Family
ID=31641551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9210589U Pending JPH0332447U (en) | 1989-08-04 | 1989-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332447U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056395A (en) * | 2008-08-29 | 2010-03-11 | Fuji Xerox Co Ltd | Exposure device and light-emitting device |
| JP2018523314A (en) * | 2015-08-06 | 2018-08-16 | 林 誼Ｌｉｎ， Ｙｉ | LED pixel point, light emitting unit, light emitting panel and display screen |
| JP2019153723A (en) * | 2018-03-06 | 2019-09-12 | 株式会社小糸製作所 | Light source module |
-
1989
- 1989-08-04 JP JP9210589U patent/JPH0332447U/ja active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056395A (en) * | 2008-08-29 | 2010-03-11 | Fuji Xerox Co Ltd | Exposure device and light-emitting device |
| JP4710936B2 (en) * | 2008-08-29 | 2011-06-29 | 富士ゼロックス株式会社 | Exposure equipment |
| JP2018523314A (en) * | 2015-08-06 | 2018-08-16 | 林 誼Ｌｉｎ， Ｙｉ | LED pixel point, light emitting unit, light emitting panel and display screen |
| JP2019153723A (en) * | 2018-03-06 | 2019-09-12 | 株式会社小糸製作所 | Light source module |
| WO2019172240A1 (en) * | 2018-03-06 | 2019-09-12 | 株式会社小糸製作所 | Light source module |
| CN111801807A (en) * | 2018-03-06 | 2020-10-20 | 株式会社小糸制作所 | Light source module |