JPH03209691A - 情報処理回路、ビットエンコードデータ記憶装置及びメモリカードのメモリアレイに再生パルスを与える方法 - Google Patents

情報処理回路、ビットエンコードデータ記憶装置及びメモリカードのメモリアレイに再生パルスを与える方法

Info

Publication number
JPH03209691A
JPH03209691A JP2306944A JP30694490A JPH03209691A JP H03209691 A JPH03209691 A JP H03209691A JP 2306944 A JP2306944 A JP 2306944A JP 30694490 A JP30694490 A JP 30694490A JP H03209691 A JPH03209691 A JP H03209691A
Authority
JP
Japan
Prior art keywords
request
regeneration
pulse
memory
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2306944A
Other languages
English (en)
Japanese (ja)
Inventor
Richard G Eikill
リチャード、グレン、アイキル
Charles P Geer
チャールズ、ポーター、ギア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH03209691A publication Critical patent/JPH03209691A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP2306944A 1989-12-13 1990-11-13 情報処理回路、ビットエンコードデータ記憶装置及びメモリカードのメモリアレイに再生パルスを与える方法 Pending JPH03209691A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/450,139 US5193165A (en) 1989-12-13 1989-12-13 Memory card refresh buffer
US450139 1989-12-13

Publications (1)

Publication Number Publication Date
JPH03209691A true JPH03209691A (ja) 1991-09-12

Family

ID=23786921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2306944A Pending JPH03209691A (ja) 1989-12-13 1990-11-13 情報処理回路、ビットエンコードデータ記憶装置及びメモリカードのメモリアレイに再生パルスを与える方法

Country Status (4)

Country Link
US (1) US5193165A (fr)
EP (1) EP0437158B1 (fr)
JP (1) JPH03209691A (fr)
DE (1) DE69025580T2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276844A (en) * 1991-08-05 1994-01-04 Ascom Autelca Ltd. Protection system for critical memory information
US5418920A (en) * 1992-04-30 1995-05-23 Alcatel Network Systems, Inc. Refresh control method and system including request and refresh counters and priority arbitration circuitry
US5638529A (en) * 1992-08-24 1997-06-10 Intel Corporation Variable refresh intervals for system devices including setting the refresh interval to zero
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
US5761703A (en) * 1996-08-16 1998-06-02 Unisys Corporation Apparatus and method for dynamic memory refresh
US5907863A (en) * 1996-08-16 1999-05-25 Unisys Corporation Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments
US6356485B1 (en) 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
US6512990B1 (en) * 2000-01-05 2003-01-28 Agilent Technologies, Inc. Distributed trigger node
US6968392B1 (en) * 2000-06-29 2005-11-22 Cisco Technology, Inc. Method and apparatus providing improved statistics collection for high bandwidth interfaces supporting multiple connections
JP2005310245A (ja) * 2004-04-20 2005-11-04 Seiko Epson Corp メモリコントローラ、半導体集積回路装置、マイクロコンピュータ及び電子機器
US7088632B2 (en) * 2004-05-26 2006-08-08 Freescale Semiconductor, Inc. Automatic hidden refresh in a dram and method therefor
US9293187B2 (en) * 2011-09-26 2016-03-22 Cisco Technology, Inc. Methods and apparatus for refreshing digital memory circuits
US9490002B2 (en) 2014-07-24 2016-11-08 Rambus Inc. Reduced refresh power

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693179A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Refresh control system
JPS6212994A (ja) * 1985-07-09 1987-01-21 Fujitsu Ltd リフレツシユ制御方式
JPS6452293A (en) * 1987-08-24 1989-02-28 Hitachi Ltd Memory built-in semiconductor integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800295A (en) * 1971-12-30 1974-03-26 Ibm Asynchronously operated memory system
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
US4172282A (en) * 1976-10-29 1979-10-23 International Business Machines Corporation Processor controlled memory refresh
US4625301A (en) * 1983-11-30 1986-11-25 Tandy Corporation Dynamic memory refresh circuit
US4625296A (en) * 1984-01-17 1986-11-25 The Perkin-Elmer Corporation Memory refresh circuit with varying system transparency
US4747082A (en) * 1984-11-28 1988-05-24 Hitachi Ltd. Semiconductor memory with automatic refresh means
JPS624577A (ja) * 1985-07-02 1987-01-10 北川工業株式会社 基板引抜具
JPS63140491A (ja) * 1986-12-02 1988-06-13 Nec Corp リフレツシユ制御方式
JPH01267896A (ja) * 1988-04-19 1989-10-25 Toshiba Corp 半導体メモリ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693179A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Refresh control system
JPS6212994A (ja) * 1985-07-09 1987-01-21 Fujitsu Ltd リフレツシユ制御方式
JPS6452293A (en) * 1987-08-24 1989-02-28 Hitachi Ltd Memory built-in semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics

Also Published As

Publication number Publication date
DE69025580D1 (de) 1996-04-04
EP0437158B1 (fr) 1996-02-28
EP0437158A2 (fr) 1991-07-17
US5193165A (en) 1993-03-09
DE69025580T2 (de) 1996-09-12
EP0437158A3 (en) 1991-12-11

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