JPH0320777B2 - - Google Patents
Info
- Publication number
- JPH0320777B2 JPH0320777B2 JP57127877A JP12787782A JPH0320777B2 JP H0320777 B2 JPH0320777 B2 JP H0320777B2 JP 57127877 A JP57127877 A JP 57127877A JP 12787782 A JP12787782 A JP 12787782A JP H0320777 B2 JPH0320777 B2 JP H0320777B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- segment
- virtual address
- page
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127877A JPS5919288A (ja) | 1982-07-22 | 1982-07-22 | 仮想記憶制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127877A JPS5919288A (ja) | 1982-07-22 | 1982-07-22 | 仮想記憶制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5919288A JPS5919288A (ja) | 1984-01-31 |
| JPH0320777B2 true JPH0320777B2 (enrdf_load_stackoverflow) | 1991-03-20 |
Family
ID=14970847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57127877A Granted JPS5919288A (ja) | 1982-07-22 | 1982-07-22 | 仮想記憶制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5919288A (enrdf_load_stackoverflow) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60204048A (ja) * | 1984-03-28 | 1985-10-15 | Hitachi Ltd | 仮想記憶方式 |
| JPS621048A (ja) * | 1985-06-04 | 1987-01-07 | Nec Corp | 仮想記憶システム |
| JPS62237547A (ja) * | 1986-04-09 | 1987-10-17 | Hitachi Ltd | アドレス変換方式 |
-
1982
- 1982-07-22 JP JP57127877A patent/JPS5919288A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5919288A (ja) | 1984-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR880011678A (ko) | 메모리 액세스 제어 장치 | |
| KR920013132A (ko) | 우선변환 참조 버퍼 | |
| JP2774862B2 (ja) | Dma制御装置および情報処理装置 | |
| JPS62100851A (ja) | 仮想記憶装置における領域管理方法 | |
| US4654791A (en) | Input/output paging mechanism in a data processor | |
| JPH0320777B2 (enrdf_load_stackoverflow) | ||
| EP2275938A1 (en) | Memory addressing and data transfer operations | |
| EP0196244A3 (en) | Cache mmu system | |
| GB2221066A (en) | Address translation for I/O controller | |
| JP2689336B2 (ja) | コンピュータシステムに於けるアダプタ用アドレス変換装置 | |
| JP2010244165A (ja) | 半導体集積回路、及び半導体集積回路の制御方法 | |
| TWI284806B (en) | Method for managing external memory of a processor and chip for managing external memory | |
| JPS6237754A (ja) | 仮想拡張記憶方式 | |
| JP3256558B2 (ja) | 電子計算機におけるアドレス変換方式 | |
| JPS6349806B2 (enrdf_load_stackoverflow) | ||
| JPS6349807B2 (enrdf_load_stackoverflow) | ||
| JPS63245545A (ja) | Dma方式 | |
| JPH047653A (ja) | 仮想記憶メモリ装置 | |
| JPS6218074B2 (enrdf_load_stackoverflow) | ||
| JPS608971A (ja) | 中央処理装置 | |
| JPH05120134A (ja) | キヤツシユメモリ実装方式 | |
| JPS63163946A (ja) | デ−タ転送装置 | |
| KR960015248A (ko) | 시스템 메모리와 데이타 버퍼램 간의 데이타 전송 방법 | |
| JPH03129543A (ja) | 主記憶装置管理方式 | |
| JPH03252856A (ja) | プログラムの処理方式 |