JPH0320541U

JPH0320541U -

Info

Publication number: JPH0320541U
Application number: JP1989080135U
Authority: JP
Priority date: 1989-07-10
Filing date: 1989-07-10
Publication date: 1991-02-28

Description

[Brief explanation of the drawing]

第１図は本考案に係る可変遅延回路の一実施例
を示す構成図、第２図はその動作を説明する為の
タイムチヤート、第３図は従来の可変遅延回路を
示す構成図、第４図はその動作を説明する為のタ
イムチヤートである。２……積分部、１０……第１のコンパレータ、
１１……第２のコンパレータ、１３……第１のゲ
ート、１４……第２のゲート、１５……第３のゲ
ート、１６……フリツプフロツプ。 FIG. 1 is a block diagram showing an embodiment of the variable delay circuit according to the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram showing a conventional variable delay circuit, and FIG. The figure is a time chart to explain the operation. 2...Integrator part, 10...First comparator,
11...second comparator, 13...first gate, 14...second gate, 15...third gate, 16...flip-flop.

Claims

[Scope of utility model registration request]

an integrating section to which the pulse signal is input; a first comparator to which the output of the integrating section and a first comparison voltage are input and comparing these voltages; and a first comparator to which the output of the integrating section and the second comparison voltage are input. a second comparator that compares these voltages; a first gate that obtains an output related to the amount of delay in the output of the first comparator at the rising edge of the pulse signal; and a first gate that obtains an output related to the amount of delay in the output of the first comparator at the rising edge of the pulse signal; a second gate that obtains an output related to the amount of delay of the output of the second comparator; a third gate that combines the outputs of the first and second gates; 1. A variable delay circuit comprising a flip-flop to which the clock terminal is input and the pulse signal is input to the data terminal.