JPS60179970U - Peak value hold circuit - Google Patents
Peak value hold circuitInfo
- Publication number
- JPS60179970U JPS60179970U JP6704484U JP6704484U JPS60179970U JP S60179970 U JPS60179970 U JP S60179970U JP 6704484 U JP6704484 U JP 6704484U JP 6704484 U JP6704484 U JP 6704484U JP S60179970 U JPS60179970 U JP S60179970U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- inverting input
- voltage amplifier
- input terminal
- peak value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のピーク値ホールド回路の例を示す回路図
、第２図は本考案のピーク値ホールド回路のブロック図
、第３図は本考案の実施例の回路図、第４図は第３図の
回路の動作を説明するための図である。
Ｎ・・！第１の電圧増幅器、Ａｏ・・・第２の電圧増幅
器、Ｓ□・・・第１のスイッチ、Ｓ２・・・第２のスイ
ッチ、Ｃ工・・・第１のコンデンサ、Ｃ２・・・第２の
コンデンサ、ＣＰ・・・比較器、ＴＭ・・・タイミング
パルス発生回路、龜・・・ゲート回路、■・・・入力信
号端子、ＯＵＴ・・・出力信号端子。Fig. 1 is a circuit diagram showing an example of a conventional peak value hold circuit, Fig. 2 is a block diagram of a peak value hold circuit of the present invention, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a circuit diagram showing an example of a conventional peak value hold circuit. FIG. 4 is a diagram for explaining the operation of the circuit in FIG. 3; N...! First voltage amplifier, Ao... second voltage amplifier, S□... first switch, S2... second switch, C engineering... first capacitor, C2... first 2 capacitor, CP...comparator, TM...timing pulse generation circuit, screw...gate circuit, ■...input signal terminal, OUT...output signal terminal.
Claims (1)
反転入力端子が接地に接続されている第１の電圧増幅器
と、 （ｂ） 非反転入力端子と接地との間に第１のコンデ
ンサと第１のスイッチの並列回路が接続されており、反
転入力端子と出力端子との間に第２のコンデンサが接続
されている第２の電圧増幅器と、 （Ｃ） 第１の電圧増幅器の出力端子と第２の電圧増
幅器の反転入力端子との間に接続された第２のスイッチ
と、 （ｄ） 非反転入力端子が第２の電圧増幅器の出力端
子に接続され、反転入力端子が前記（ａ）項の入力信号
端子に接続されている比較器と、 （ｅ） 前記比較器の出力によりトリガされ、前記入
力信号端子から入力される信号の周期より充分に長い周
期のタイミングパルスを発生することにより前記第１、
第２のスイッチを同時に開閉させる開閉信号を発生させ
るパルス発生回路と、 から成ることを特徴とするピーク値ホールド回路。[Claims for Utility Model Registration] (a) A non-inverting input terminal is connected to an input signal terminal,
(b) a first voltage amplifier having an inverting input terminal connected to ground; (b) a parallel circuit of a first capacitor and a first switch connected between the non-inverting input terminal and ground; a second voltage amplifier having a second capacitor connected between the terminal and the output terminal; (C) connected between the output terminal of the first voltage amplifier and the inverting input terminal of the second voltage amplifier; (d) a comparator whose non-inverting input terminal is connected to the output terminal of the second voltage amplifier and whose inverting input terminal is connected to the input signal terminal of paragraph (a); (e) the first,
A peak value hold circuit comprising: a pulse generation circuit that generates an opening/closing signal that simultaneously opens and closes a second switch;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6704484U JPS60179970U (en) | 1984-05-10 | 1984-05-10 | Peak value hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6704484U JPS60179970U (en) | 1984-05-10 | 1984-05-10 | Peak value hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60179970U true JPS60179970U (en) | 1985-11-29 |
Family
ID=30600496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6704484U Pending JPS60179970U (en) | 1984-05-10 | 1984-05-10 | Peak value hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60179970U (en) |
-
1984
- 1984-05-10 JP JP6704484U patent/JPS60179970U/en active Pending
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