JPS6147558U

JPS6147558U - Image signal processing circuit

Info

Publication number: JPS6147558U
Application number: JP13154384U
Authority: JP
Inventors: 勝山村
Original assignee: 株式会社東芝
Priority date: 1984-08-30
Filing date: 1984-08-30
Publication date: 1986-03-29

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の画信号処理回路のブロック図、第２図ａ
” ｅおよび第３図ａ−ｅは第１図に示した回路の動
作を説明するためのタイミングチャート、第４図は本考
案の画信号処理回路のブロック図、第５図はその遅延回
路およびゲート回路の実例を示す回路図、第６図ａ ”
ｎは第５図に示した回路の動作を説明するためのタイ
ミングチャートである。１１．１２，１３・・・比較器、１４．１５・・・１ビ
ット遅延回路、１６・・・ゲート回路、１７・・・クロ
ック端子、１８・・・入力樺子、１９・・・出力端子。Figure 1 is a block diagram of a conventional image signal processing circuit, Figure 2a
"e and Figures 3a-e are timing charts for explaining the operation of the circuit shown in Figure 1, Figure 4 is a block diagram of the image signal processing circuit of the present invention, and Figure 5 is its delay circuit and Circuit diagram showing an example of a gate circuit, Fig. 6a ”
5. n is a timing chart for explaining the operation of the circuit shown in FIG. 11.12, 13... Comparator, 14.15... 1-bit delay circuit, 16... Gate circuit, 17... Clock terminal, 18... Input Sashiko, 19... Output terminal .

Claims

[Claims for Utility Model Registration] Comparing the analog image signal with the first threshold level
a first comparator that generates a binary signal; and a first comparator that generates a second binary signal by comparing the analog image signal with a second threshold level higher than the first threshold level. Second to do
a third comparator that compares the analog image signal with a third threshold level higher than the second threshold level to generate a third binarized signal; a first delay circuit that delays the second binary signal by a time corresponding to the period according to a clock pulse having a period corresponding to the minimum pixel of the analog image signal; and the third binary signal; a second delay circuit that delays the image by the time according to the clock pulse; and a second delay circuit that calculates the output of the first comparator and each output of the first and second delay circuits to correspond to the analog image signal. An image signal processing circuit comprising a gate circuit that outputs a digital image signal.