JPS59138966U - Binarization device - Google Patents
Binarization deviceInfo
- Publication number
- JPS59138966U JPS59138966U JP3182683U JP3182683U JPS59138966U JP S59138966 U JPS59138966 U JP S59138966U JP 3182683 U JP3182683 U JP 3182683U JP 3182683 U JP3182683 U JP 3182683U JP S59138966 U JPS59138966 U JP S59138966U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- signal
- delay circuit
- output signal
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Image Input (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の２値化装置の実施例、第２図は第１図の
装置の動作説明図、第３図は本考案による２値化装置の
実施例、第４図、第５図は第３図の装置の動作説明図で
ある。
１、 １３． １４・・・比較器、１０． １１． １
２・・・増巾器、１５．１６・・・遅延回路。FIG. 1 is an embodiment of a conventional binarization device, FIG. 2 is an explanatory diagram of the operation of the device in FIG. 1, FIG. 3 is an embodiment of a binarization device according to the present invention, and FIGS. 4 and 5. 3 is an explanatory diagram of the operation of the apparatus shown in FIG. 3. FIG. 1, 13. 14... Comparator, 10. 11. 1
2...Amplifier, 15.16...Delay circuit.
Claims (1)
の遅延回路を介して入力とする第２の増巾器と、前記原
信号を第２の遅延回路を介して入力とする第３の増巾器
と、前記第１の増巾器の出力信号に所定電圧を加算した
信号と第２の増巾器の出力信号とを比較する第１の比較
器と、前記第３の増巾器の出力信号に所定電圧を加算し
た信号と第２の増巾器の出力信号とを比較する第２の比
較器と、第１、第２の比較器の論理和をとって２値化信
号を出力するゲート回路とを備え、前記第１、第３の増
巾器の増巾器を前記第２の増巾器の増巾器より大きく設
定し、かつ前記第１の遅延回 −路の遅延時間を前
記第２の遅延回路の遅延時間よりも小さく設定したこと
を特徴とする２値化装置。a first amplifier to which the original signal is input;
a second amplifier that inputs the original signal through a second delay circuit; a third amplifier that inputs the original signal through a second delay circuit; and an output signal of the first amplifier. a first comparator that compares a signal obtained by adding a predetermined voltage to the output signal of the second amplifier; a first comparator that compares a signal obtained by adding a predetermined voltage to the output signal of the third amplifier; A second comparator that compares the output signal of the width converter, and a gate circuit that takes the logical sum of the first and second comparators and outputs a binary signal, and the first and third The amplifier of the amplifier is set larger than the amplifier of the second amplifier, and the delay time of the first delay circuit is set smaller than the delay time of the second delay circuit. A binarization device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3182683U JPS59138966U (en) | 1983-03-04 | 1983-03-04 | Binarization device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3182683U JPS59138966U (en) | 1983-03-04 | 1983-03-04 | Binarization device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59138966U true JPS59138966U (en) | 1984-09-17 |
Family
ID=30162667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3182683U Pending JPS59138966U (en) | 1983-03-04 | 1983-03-04 | Binarization device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59138966U (en) |
-
1983
- 1983-03-04 JP JP3182683U patent/JPS59138966U/en active Pending
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