JPH0319259A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0319259A
JPH0319259A JP15431889A JP15431889A JPH0319259A JP H0319259 A JPH0319259 A JP H0319259A JP 15431889 A JP15431889 A JP 15431889A JP 15431889 A JP15431889 A JP 15431889A JP H0319259 A JPH0319259 A JP H0319259A
Authority
JP
Japan
Prior art keywords
resin film
pattern
region
resin
resin solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15431889A
Other languages
Japanese (ja)
Other versions
JP2513033B2 (en
Inventor
Ryuichi Okamura
龍一 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1154318A priority Critical patent/JP2513033B2/en
Publication of JPH0319259A publication Critical patent/JPH0319259A/en
Application granted granted Critical
Publication of JP2513033B2 publication Critical patent/JP2513033B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve reliability and easily control the dripping quantity of a resin solution by providing a 20-40mum thick pattern containing a region for forming a resin film. CONSTITUTION:A side wall of 20-40mum in thickness forms a goldplated pattern 3 by using gold-plating, so as to surround a region for forming a resin film 4 on a semiconductor chip 1. Resin solution is dropped on the region for forming the resin film 4 in the pattern 3, thereby completely covering the inside of the pattern 3. Since the pattern 3 serves as a bank, the resin solution covers only the pattern 3 and does not stretch outside. Next a resin film 4 is formed by heat treatment. Hence the region for forming the resin film 4 is completely covered, so that the reliability is improved and the control of the dripping quantity of resin solution is facilitated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置のα線によるンフトエラ一対策に関
し、半導体装置表面の樹脂膜を形威すべき領域の構造に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to measures against fatigue caused by alpha rays in semiconductor devices, and relates to the structure of a region on the surface of a semiconductor device where a resin film is to be formed.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の実施例を第5図,第6図に
示す. 第5図は従来の実施例の平面図であり、第6図は第5図
C−C’断面図である。構或は、半導体集積回路の構成
された半導体チップ1電源及び信号の入出力バッド2,
α線によるソフトエラ一対策として半導体チップl上に
形成する樹脂膜4,半導体装置上の樹脂膜を形成すべき
領域8である。
Examples of conventional semiconductor devices of this type are shown in FIGS. 5 and 6. FIG. 5 is a plan view of the conventional embodiment, and FIG. 6 is a sectional view taken along line CC' in FIG. Alternatively, a semiconductor chip configured with a semiconductor integrated circuit 1 power supply and signal input/output pad 2,
These are the resin film 4 formed on the semiconductor chip l as a countermeasure against soft errors caused by α rays, and the region 8 where the resin film on the semiconductor device is to be formed.

次に第5図及び第6図を用いて従来の実施例を説明する
Next, a conventional embodiment will be explained using FIGS. 5 and 6.

半導体装置において、メモリー領域等の樹脂膜を形戒す
べき領域8上に、α線によるンフトエラ一対策等により
ポリイミド等の樹脂溶液を1点あるいは多点に滴下し、
200〜300℃の熱処理を加えて厚さ30〜300μ
mの樹脂膜4を形成する。
In a semiconductor device, a resin solution such as polyimide is dropped at one point or multiple points on an area 8 where a resin film such as a memory area should be protected, as a measure against erectile dysfunction caused by alpha rays.
Add heat treatment at 200-300℃ to a thickness of 30-300μ
A resin film 4 of m is formed.

ここで、樹脂溶液を滴下した際に、滴下方法の不具合あ
るいは滴下量の多少により、樹脂膜4が電源及び配線の
入出力パッド2上まで広がってしまう。あるいは樹脂膜
を形威すべき領域8上を完全に覆わない等の不具合が生
じる。
Here, when the resin solution is dropped, the resin film 4 spreads onto the input/output pad 2 for the power supply and wiring due to a defect in the dropping method or the amount dropped. Alternatively, problems such as not completely covering the region 8 where the resin film should be applied may occur.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置は、α線によるンフトエラ一
対策として半導体表面に樹脂膜を形成する際、樹脂溶液
の滴下方法あるいは滴下量等の不具合により、樹脂膜が
電源及び信号の入出力パッド上に広がってしまう。ある
いは、樹脂膜を形成すべき領域上を完全に覆わない等の
不具合が生じ、半導体装置の信頼性が低下するという欠
点がある。
In the conventional semiconductor device described above, when a resin film is formed on the semiconductor surface as a countermeasure against alpha-ray radiation, due to a problem with the method or amount of dropping of the resin solution, the resin film may end up on the power supply and signal input/output pads. It will spread. Alternatively, problems such as not completely covering the region where the resin film is to be formed occur, resulting in a disadvantage that the reliability of the semiconductor device is reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、樹脂膜を形威すべき領域を囲む
厚さ20〜40μmのパターンを有し、そのパターン内
に樹脂膜を形成する。
The semiconductor device of the present invention has a pattern with a thickness of 20 to 40 μm surrounding a region where a resin film is to be formed, and the resin film is formed within the pattern.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の実施例1の平面図、第2図は第1図A
−A’断面図である.構或は半導体集積回路の形威され
た半導体チップ1、電源及び信号の入出力パッド2、樹
脂膜を形威すべき領域を囲むパターン3、α線によるソ
フトエラ一対策として半導体チップ1上に形成する樹脂
膜4である.次に第1図,第2図を用いて本発明の実施
例1を説明する. 半導体集積回路の形成された半導体チップ1上にメモリ
ー領域等の樹脂膜を形成すべき領域を囲むように、電解
金メッキを用いて厚さ20〜40μm,幅50〜100
μm程度の側壁が垂直な金メッキパターン3を形成する
。パターン3は最上層配線を形戒する際に同時に形成し
てもよく電源配線等と共用であってもよい。
Figure 1 is a plan view of Embodiment 1 of the present invention, and Figure 2 is Figure 1A.
-A' cross-sectional view. A semiconductor chip 1 in which a structure or a semiconductor integrated circuit is formed, a power supply and signal input/output pad 2, a pattern 3 surrounding the area where a resin film is to be formed, and a pattern 3 formed on the semiconductor chip 1 as a countermeasure against soft errors caused by alpha rays. This is the resin film 4. Next, Embodiment 1 of the present invention will be explained using FIGS. 1 and 2. Electrolytic gold plating is used to surround areas where a resin film is to be formed, such as a memory area, on the semiconductor chip 1 on which a semiconductor integrated circuit is formed, to a thickness of 20 to 40 μm and a width of 50 to 100 μm.
A gold plating pattern 3 with vertical side walls of about μm is formed. The pattern 3 may be formed at the same time as forming the top layer wiring, or may be used in common with the power supply wiring, etc.

次にパターン3内の樹脂膜を形成すべき領域上の1点あ
るいは多点にポリイミド等の樹脂溶液を滴下する。この
時パターン3内を完全に覆うだけの量を滴下するが、パ
ターン3が堤防となり、樹脂溶液はパターン3の外には
広がらない。
Next, a resin solution such as polyimide is dropped at one point or multiple points on the region in the pattern 3 where a resin film is to be formed. At this time, an amount sufficient to completely cover the inside of the pattern 3 is dropped, but the pattern 3 becomes an embankment and the resin solution does not spread outside the pattern 3.

次に200〜300℃程度の熱処理を加え、樹脂膜4を
形成する。樹脂膜4の厚さは30〜300μm程度であ
る. 実施例1は厚さ20μm以上の良好な形状のパターンが
得られるノポラ,ク樹脂系の超厚膜レジストを用いて選
択的に電解金メッキを行い、横広がりがなく側壁が垂直
な厚さ20〜40μmの金メッキパターンが得られるこ
とに着目しているが、パターン3は金メッキ以外の方法
及び材質で形威されても、もちろんかまわない。
Next, a heat treatment is applied at about 200 to 300°C to form a resin film 4. The thickness of the resin film 4 is approximately 30 to 300 μm. In Example 1, electrolytic gold plating was selectively performed using a Nopola resin-based ultra-thick film resist that yields a well-shaped pattern with a thickness of 20 μm or more. Although attention is focused on obtaining a 40 μm gold plating pattern, pattern 3 may of course be formed using a method and material other than gold plating.

〔実施例2〕 第3図は本発明の実施例2の平面図であり、第4図は第
3図B−B’断面図である。構成は半導体集積回路の形
成されたチップ1電源及び信号の入出力パッド2、第1
の電源の配線パターン5、第2の電源の配線パターン6
、第3の電源の配線パターン7、α線によるソフトエラ
一対策のために形成する樹脂膜4である。
[Embodiment 2] FIG. 3 is a plan view of Embodiment 2 of the present invention, and FIG. 4 is a sectional view taken along the line BB' in FIG. The structure consists of a chip on which a semiconductor integrated circuit is formed, a power supply and signal input/output pad 2, a first
wiring pattern 5 of the power supply, wiring pattern 6 of the second power supply
, a wiring pattern 7 for the third power supply, and a resin film 4 formed to prevent soft errors caused by alpha rays.

次に第3図,第4図を用いて本発明の実施例2を説明す
る。
Next, a second embodiment of the present invention will be described using FIGS. 3 and 4.

半導体集積回路の形成された半導体チップlの最上層配
線を金メッキ等を用い厚さ20〜40μm程度に形成す
る。この時、第1の電源の配線パターン5,第2の電源
の配線パターン6,第3の電源の配線パターン7はそれ
ぞれ樹脂膜を形威すべき領域を囲む様に配置されている
.次に樹脂膜を形成すべき領域上の1点あるいは多点に
ポリイミド等の樹脂溶液を滴下する。このとき、樹脂膜
を形成すべき領域を完全に覆うだけの量の樹膜溶液を滴
下するが第1の電源の配線パターン5,第2の電源の配
線パターン6,第3の電源の配線パターン7が2重構造
の堤防となり、樹脂溶液は電源配線のパターンの外には
広がらない。
The uppermost layer wiring of the semiconductor chip l on which the semiconductor integrated circuit is formed is formed to a thickness of about 20 to 40 μm using gold plating or the like. At this time, the wiring pattern 5 for the first power supply, the wiring pattern 6 for the second power supply, and the wiring pattern 7 for the third power supply are respectively arranged so as to surround the area where the resin film is to be formed. Next, a resin solution such as polyimide is dropped at one point or multiple points on the area where the resin film is to be formed. At this time, enough resin solution is dropped to completely cover the area where the resin film is to be formed. 7 becomes a double-structured embankment, and the resin solution does not spread outside the power supply wiring pattern.

次に200〜300℃程度の熱処理を加え、厚さ30〜
300μm程度の樹脂膜を形成する。
Next, heat treatment is applied at about 200 to 300℃, and the thickness is 30 to 30℃.
A resin film of about 300 μm is formed.

この様に、樹脂膜を形成すべき領域を2重以上のパター
ンで囲むことにより実施例1に比べ樹脂溶液の滴下方法
及び滴下量の制御が容易になり半導体装置の信頼性がさ
らに向上する。
In this way, by surrounding the area where the resin film is to be formed with two or more patterns, it becomes easier to control the dropping method and amount of the resin solution than in Example 1, and the reliability of the semiconductor device is further improved.

〔発明の効果〕 以上説明した様に本発明は樹脂膜を形成すべき領域を囲
むパターンを有しており、そのパターンを堤防として、
パターン内にのみ樹脂膜を形成することにより、樹脂膜
の広がりを抑え、かつ樹脂膜を形成すべき領域を完全に
覆うことができ、半導体装置の信頼性を向上させること
ができる。また樹脂溶液の滴下方法及び滴下量の制御が
容易になる。
[Effects of the Invention] As explained above, the present invention has a pattern surrounding the area where the resin film is to be formed, and the pattern is used as an embankment.
By forming the resin film only within the pattern, it is possible to suppress the spread of the resin film and completely cover the region where the resin film is to be formed, thereby improving the reliability of the semiconductor device. Furthermore, it becomes easier to control the method and amount of dropping the resin solution.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例1の平面図、第2図は第1図A
−A’断面図である。第3図は本発明の実施例2の平面
図、第4図は第3図B−B’断面図である。第5図は従
来の実施例の平面図、第6図は第5図のC−C’断面図
である. 1・・・・・・半導体チップ、2・・・・・・電源及び
信号の入出力パッド、3・・・・・・樹脂膜を形成すべ
き領域を囲むパターン、4・・・・・・樹脂膜、5・・
・・・・第1の電源の配線パターン、6・・・・・・第
2の電源の配線パターン、7・・・・・・第3の電源の
配線パターン、8・・・・・・樹脂膜を形成すべき領域
Figure 1 is a plan view of Embodiment 1 of the present invention, and Figure 2 is Figure 1A.
-A' sectional view. FIG. 3 is a plan view of a second embodiment of the present invention, and FIG. 4 is a sectional view taken along line BB' in FIG. FIG. 5 is a plan view of the conventional embodiment, and FIG. 6 is a sectional view taken along line CC' in FIG. 1... Semiconductor chip, 2... Power supply and signal input/output pad, 3... Pattern surrounding the area where the resin film is to be formed, 4... Resin film, 5...
... Wiring pattern of first power supply, 6 ... Wiring pattern of second power supply, 7 ... Wiring pattern of third power supply, 8 ... Resin Area where a film should be formed.

Claims (1)

【特許請求の範囲】[Claims] 表面に樹脂膜を有する半導体装置において、半導体装置
上で樹脂膜を形成すべき領域を囲む厚さ20〜40μm
のパターンを有し、そのパターン内に樹脂膜を形成する
ことを特徴とする半導体装置。
In a semiconductor device having a resin film on the surface, a thickness of 20 to 40 μm surrounding the area where the resin film is to be formed on the semiconductor device.
What is claimed is: 1. A semiconductor device having a pattern, and a resin film formed within the pattern.
JP1154318A 1989-06-15 1989-06-15 Semiconductor device Expired - Lifetime JP2513033B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1154318A JP2513033B2 (en) 1989-06-15 1989-06-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1154318A JP2513033B2 (en) 1989-06-15 1989-06-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0319259A true JPH0319259A (en) 1991-01-28
JP2513033B2 JP2513033B2 (en) 1996-07-03

Family

ID=15581508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1154318A Expired - Lifetime JP2513033B2 (en) 1989-06-15 1989-06-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2513033B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530278A (en) * 1995-04-24 1996-06-25 Xerox Corporation Semiconductor chip having a dam to prevent contamination of photosensitive structures thereon
JPH08335594A (en) * 1995-06-08 1996-12-17 Fujitsu Ten Ltd Sealing structure and sealing method of semiconductor chip
US7804161B2 (en) * 2007-03-30 2010-09-28 Oki Semiconductor Co., Ltd. Semiconductor device and dam for resin
US8018057B2 (en) * 2007-02-21 2011-09-13 Seiko Epson Corporation Semiconductor device with resin layers and wirings and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776869A (en) * 1980-10-31 1982-05-14 Fujitsu Ltd Semiconductor device
JPS5776868A (en) * 1980-10-30 1982-05-14 Fujitsu Ltd Forming method for resin protected film
JPS5885553A (en) * 1981-11-18 1983-05-21 Nec Corp Semiconductor device
JPS58107657A (en) * 1981-12-21 1983-06-27 Nec Corp Semiconductor device
JPS58111351A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Radiation shielding type semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776868A (en) * 1980-10-30 1982-05-14 Fujitsu Ltd Forming method for resin protected film
JPS5776869A (en) * 1980-10-31 1982-05-14 Fujitsu Ltd Semiconductor device
JPS5885553A (en) * 1981-11-18 1983-05-21 Nec Corp Semiconductor device
JPS58107657A (en) * 1981-12-21 1983-06-27 Nec Corp Semiconductor device
JPS58111351A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Radiation shielding type semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530278A (en) * 1995-04-24 1996-06-25 Xerox Corporation Semiconductor chip having a dam to prevent contamination of photosensitive structures thereon
JPH08335594A (en) * 1995-06-08 1996-12-17 Fujitsu Ten Ltd Sealing structure and sealing method of semiconductor chip
US8018057B2 (en) * 2007-02-21 2011-09-13 Seiko Epson Corporation Semiconductor device with resin layers and wirings and method for manufacturing the same
US7804161B2 (en) * 2007-03-30 2010-09-28 Oki Semiconductor Co., Ltd. Semiconductor device and dam for resin
US8432025B2 (en) 2007-03-30 2013-04-30 Lapis Semiconductor Co., Ltd. Semiconductor device and plurality of dams

Also Published As

Publication number Publication date
JP2513033B2 (en) 1996-07-03

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