JPS558061A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS558061A JPS558061A JP8074778A JP8074778A JPS558061A JP S558061 A JPS558061 A JP S558061A JP 8074778 A JP8074778 A JP 8074778A JP 8074778 A JP8074778 A JP 8074778A JP S558061 A JPS558061 A JP S558061A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- metal
- melting point
- employing
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: For increasing elements in density, to make an IC employing the wiring of a high melting point metal such as Mo and W, of a double layer film of the metal employing the bonding pads or wiring of Al or Al-Si, and Al-Si.
CONSTITUTION: A first layer wiring including a gate wiring 8 and a second layer wiring including the lead-out wire from source and drain diffusion ranges are made of high melting point metals such as Mo and W. The bonding pad to be deposited on said wiring layers is a two-layer film of Al, Al-Si or the same kind of metal as used for said wiring layers, an Al-Si. Thereby, pierce-through does which occurs frequently when Al wiring is adopted does not occur so that diffusion range is not required to be provided deep, and integration degree is increased.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8074778A JPS558061A (en) | 1978-07-03 | 1978-07-03 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8074778A JPS558061A (en) | 1978-07-03 | 1978-07-03 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS558061A true JPS558061A (en) | 1980-01-21 |
Family
ID=13726988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8074778A Pending JPS558061A (en) | 1978-07-03 | 1978-07-03 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS558061A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150076551A1 (en) * | 2012-06-07 | 2015-03-19 | Michael A. Tischler | Methods of fabricating wafer-level flip chip device packages |
US9054290B2 (en) | 2010-06-29 | 2015-06-09 | Cooledge Lighting Inc. | Electronic devices with yielding substrates |
US9107272B2 (en) | 2010-01-04 | 2015-08-11 | Cooledge Lighting Inc. | Failure mitigation in arrays of light-emitting devices |
US9179510B2 (en) | 2009-06-27 | 2015-11-03 | Cooledge Lighting Inc. | High efficiency LEDs and LED lamps |
-
1978
- 1978-07-03 JP JP8074778A patent/JPS558061A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9179510B2 (en) | 2009-06-27 | 2015-11-03 | Cooledge Lighting Inc. | High efficiency LEDs and LED lamps |
US9107272B2 (en) | 2010-01-04 | 2015-08-11 | Cooledge Lighting Inc. | Failure mitigation in arrays of light-emitting devices |
US9054290B2 (en) | 2010-06-29 | 2015-06-09 | Cooledge Lighting Inc. | Electronic devices with yielding substrates |
US9252373B2 (en) | 2010-06-29 | 2016-02-02 | Cooledge Lighting, Inc. | Electronic devices with yielding substrates |
US9426860B2 (en) | 2010-06-29 | 2016-08-23 | Cooledge Lighting, Inc. | Electronic devices with yielding substrates |
US20150076551A1 (en) * | 2012-06-07 | 2015-03-19 | Michael A. Tischler | Methods of fabricating wafer-level flip chip device packages |
US9214615B2 (en) * | 2012-06-07 | 2015-12-15 | Cooledge Lighting Inc. | Methods of fabricating wafer-level flip chip device packages |
US9231178B2 (en) | 2012-06-07 | 2016-01-05 | Cooledge Lighting, Inc. | Wafer-level flip chip device packages and related methods |
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