JPH0312502B2 - - Google Patents
Info
- Publication number
- JPH0312502B2 JPH0312502B2 JP56215031A JP21503181A JPH0312502B2 JP H0312502 B2 JPH0312502 B2 JP H0312502B2 JP 56215031 A JP56215031 A JP 56215031A JP 21503181 A JP21503181 A JP 21503181A JP H0312502 B2 JPH0312502 B2 JP H0312502B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- latch
- data signal
- sending
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21503181A JPS58115956A (ja) | 1981-12-28 | 1981-12-28 | デ−タ受信方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21503181A JPS58115956A (ja) | 1981-12-28 | 1981-12-28 | デ−タ受信方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58115956A JPS58115956A (ja) | 1983-07-09 |
| JPH0312502B2 true JPH0312502B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-02-20 |
Family
ID=16665598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21503181A Granted JPS58115956A (ja) | 1981-12-28 | 1981-12-28 | デ−タ受信方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58115956A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583810A (en) * | 1991-01-31 | 1996-12-10 | Interuniversitair Micro-Elektronica Centrum Vzw | Method for programming a semiconductor memory device |
| US6243293B1 (en) | 1992-01-29 | 2001-06-05 | Interuniversitair Micro-Elektronica Centrum | Contacted cell array configuration for erasable and programmable semiconductor memories |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010466B2 (ja) * | 1978-01-27 | 1985-03-18 | 株式会社東芝 | メツセ−ジ伝送方式 |
-
1981
- 1981-12-28 JP JP21503181A patent/JPS58115956A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58115956A (ja) | 1983-07-09 |