JPS6464049A - Degeneration controller for buffer device - Google Patents

Degeneration controller for buffer device

Info

Publication number
JPS6464049A
JPS6464049A JP62221333A JP22133387A JPS6464049A JP S6464049 A JPS6464049 A JP S6464049A JP 62221333 A JP62221333 A JP 62221333A JP 22133387 A JP22133387 A JP 22133387A JP S6464049 A JPS6464049 A JP S6464049A
Authority
JP
Japan
Prior art keywords
error
circuit
degeneration
control information
valid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62221333A
Other languages
Japanese (ja)
Inventor
Hitoshi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62221333A priority Critical patent/JPS6464049A/en
Publication of JPS6464049A publication Critical patent/JPS6464049A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To surely report the occurrence of degeneration despite such a fault with which it is regarded that the degeneration control information is always kept set, by reporting the occurrence of an error regardless of the state of a DG bit in case the degeneration control information is not set. CONSTITUTION:When an error is detected out of the entry data read out of a buffer device 1 is detected by an error detecting circuit 4, the output of a 1st AND circuit 5 is valid as long as the degeneration control information (DG bit) 3 which is read out simultaneously with detection of said error is not set. Thus the error is reported via an error reporting signal line 9. While a 2nd AND circuit 7 is valid when a degeneration control information register 6 is not set at detection of the error. Thus the error is reported via an OR circuit 8 and the line 9. At the same time, the register 6 is set and the output of the circuit 7 is never valid to the subsequent errors.
JP62221333A 1987-09-04 1987-09-04 Degeneration controller for buffer device Pending JPS6464049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62221333A JPS6464049A (en) 1987-09-04 1987-09-04 Degeneration controller for buffer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62221333A JPS6464049A (en) 1987-09-04 1987-09-04 Degeneration controller for buffer device

Publications (1)

Publication Number Publication Date
JPS6464049A true JPS6464049A (en) 1989-03-09

Family

ID=16765162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62221333A Pending JPS6464049A (en) 1987-09-04 1987-09-04 Degeneration controller for buffer device

Country Status (1)

Country Link
JP (1) JPS6464049A (en)

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