JPS5667426A - Processing system for failed data - Google Patents

Processing system for failed data

Info

Publication number
JPS5667426A
JPS5667426A JP14276179A JP14276179A JPS5667426A JP S5667426 A JPS5667426 A JP S5667426A JP 14276179 A JP14276179 A JP 14276179A JP 14276179 A JP14276179 A JP 14276179A JP S5667426 A JPS5667426 A JP S5667426A
Authority
JP
Japan
Prior art keywords
circuit
output
data
register
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14276179A
Other languages
Japanese (ja)
Inventor
Hiromasa Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14276179A priority Critical patent/JPS5667426A/en
Publication of JPS5667426A publication Critical patent/JPS5667426A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To proceed the normal data transfer without report of failure to the processor, when an error is detected to the output of one register, by making duplex buffer registers for input data storage and comparing the output of both the registers for check.
CONSTITUTION: A transfer data is simultaneously stored in the 1nst and 2nd registers 6, 7 in a normal timing T1, and stored data is given to incorrect data detection circuits 11, 12, comparison circuit 13 and a selection circuit 14. Further, the output of registers 6, 7 is compared by bits at the circuit 13, and the result is set to the 3rd register 38. Further, incorrect data detection signals 16, 17 are fed to AND gates 19W21 after they are inspected at the circuits 11 and 12, and when incorrectness is detected, a failure report signal 49 is output via an interface control circuit 47 to a data processor 200. Further, the output of a register 38 is fed to the circuit 47, the selection circuit output signal 33 selected at the circuit 14 is fed to the circuit 47, enabling to transfer the normal data when an error in one register 6 or 7 is detected.
COPYRIGHT: (C)1981,JPO&Japio
JP14276179A 1979-11-06 1979-11-06 Processing system for failed data Pending JPS5667426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14276179A JPS5667426A (en) 1979-11-06 1979-11-06 Processing system for failed data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14276179A JPS5667426A (en) 1979-11-06 1979-11-06 Processing system for failed data

Publications (1)

Publication Number Publication Date
JPS5667426A true JPS5667426A (en) 1981-06-06

Family

ID=15322957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14276179A Pending JPS5667426A (en) 1979-11-06 1979-11-06 Processing system for failed data

Country Status (1)

Country Link
JP (1) JPS5667426A (en)

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