JPH023308B2 - - Google Patents
Info
- Publication number
- JPH023308B2 JPH023308B2 JP57030772A JP3077282A JPH023308B2 JP H023308 B2 JPH023308 B2 JP H023308B2 JP 57030772 A JP57030772 A JP 57030772A JP 3077282 A JP3077282 A JP 3077282A JP H023308 B2 JPH023308 B2 JP H023308B2
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- silicon nitride
- film
- silicon
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 description 48
- 150000004767 nitrides Chemical class 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は特性の改善された薄膜構造の電界効果
トランジスタその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor having a thin film structure with improved characteristics.
第１図ａは従来のこの種の電界効果トランジス
タ（以下FETという。）の構成を示す縦断面図、
第１図ｂはその平面図で、１はガラス基板、２は
クロム（Cr）で形成されたゲート電極、３は厚
さ約3000Åのシリコン窒化膜からなるゲート絶縁
膜、４はグロー放電で形成されたアモルフアスシ
リコン層、５ａおよび５ｂはそれぞれアモルフア
スシリコン層４の表面上にゲート電極２に対応す
る部分を挾んで設けられ、アルミニウムAlで形
成されたソースおよびドレイン電極、６は表面保
護膜である。なお、第１図ｂでは基板１および表
面保護膜６は省略されている。 Figure 1a is a vertical cross-sectional view showing the configuration of a conventional field effect transistor (hereinafter referred to as FET) of this type.
Figure 1b is a plan view of the same, where 1 is a glass substrate, 2 is a gate electrode made of chromium (Cr), 3 is a gate insulating film made of a silicon nitride film with a thickness of about 3000 Å, and 4 is formed by glow discharge. The amorphous silicon layers 5a and 5b are respectively provided on the surface of the amorphous silicon layer 4, sandwiching a portion corresponding to the gate electrode 2, source and drain electrodes made of aluminum Al, and 6 a surface protective film. It is. Note that the substrate 1 and the surface protection film 6 are omitted in FIG. 1b.
このような構成のFETにおいてドレイン５ｂ
とソース５ａとの間に10Vの電圧が印加される
が、アモルフアスシリコン層４はバンドギヤツプ
が通常のシリコンに比して広いので、光が当つて
もキヤリアが励起される確率は低い。従つて、光
を当てた状態でも抵抗は非常に高く、電流はほと
んど流れない。ゲート２に５〜20V程度の正電圧
が印加されると、ゲート絶縁膜３を介してアモル
フアスシリコン層４の界面に電界が加えられチヤ
ネルが開いて、ドレイン５ｂ、ソース５ａ間が導
通できるようになり電流が流れはじめる。このと
き、従来のFETではゲート絶縁膜３が窒化膜で
あるので、アモルフアスシリコン層４との界面に
多数の準位が形成され、これに対するキヤリアの
トラツプや放出のため、FETの電気特性の再現
性に問題があり、長時間でのドリフトなど実用上
問題が多い。また、アモルフアスシリコン層をレ
ーザなどのエネルギー線で多結晶化してキヤリア
モビリテイの増加をはかるような場合には、さら
に電気特性上の上述の問題点が顕著になつてく
る。 In an FET with such a configuration, the drain 5b
A voltage of 10 V is applied between the amorphous silicon layer 4 and the source 5a, but since the bandgap of the amorphous silicon layer 4 is wider than that of ordinary silicon, there is a low probability that carriers will be excited even when exposed to light. Therefore, even when exposed to light, the resistance is extremely high and almost no current flows. When a positive voltage of about 5 to 20 V is applied to the gate 2, an electric field is applied to the interface of the amorphous silicon layer 4 through the gate insulating film 3, opening a channel and establishing conduction between the drain 5b and the source 5a. current begins to flow. At this time, in the conventional FET, since the gate insulating film 3 is a nitride film, a large number of levels are formed at the interface with the amorphous silicon layer 4, and carriers are trapped and released in response to this, which affects the electrical characteristics of the FET. There are problems with reproducibility and there are many practical problems such as drift over a long period of time. Furthermore, when an amorphous silicon layer is polycrystallized using energy beams such as a laser to increase carrier mobility, the above-mentioned problems regarding electrical characteristics become even more pronounced.
またシリコン酸化膜（SiO2）がシリコン（Si）
とのよい界面特性を与え、ゲート絶縁膜としてシ
リコン窒化膜より優れていることは経験的事実と
して知られていたが、スパツタやCVD法を用い
窒化膜上に酸化膜を形成する方法ではあまりよい
界面特性を得ることではできなかつた。 Also, silicon oxide film (SiO 2 ) is silicon (Si).
It has been empirically known that silicon nitride is superior to silicon nitride as a gate insulating film because it provides good interfacial properties with silicon nitride, but methods of forming an oxide film on a nitride film using sputtering or CVD methods are not so good. This could not be achieved by obtaining interfacial properties.
本発明は以上のような点に鑑みてなされたもの
で、基板上に窒化シリコン膜を形成した後、該窒
化シリコン膜の表面を酸素プラズマにさらしてあ
るいは酸素雰囲気中で該窒化シリコン膜表面にレ
ーザ光を照射して該窒化膜表面を酸化しその後形
成された酸化膜上にアモルフアスシリコンまたは
多結晶シリコンからなる活性領域を形成するよう
にすることにより、窒化膜の緻密さ、誘電率の大
きさという特性を失うことなく、活性領域と絶縁
層との界面特性をより向上できるとともに低温酸
化が可能となり、特性の安定した信頼性の高い
FETを再現性よく製造できるFETの製造方法を
提供することを目的としている。 The present invention has been made in view of the above points, and after forming a silicon nitride film on a substrate, the surface of the silicon nitride film is exposed to oxygen plasma or in an oxygen atmosphere. By irradiating the nitride film with laser light to oxidize the surface of the nitride film and then forming an active region made of amorphous silicon or polycrystalline silicon on the oxide film, the density and dielectric constant of the nitride film can be improved. The interface characteristics between the active region and the insulating layer can be further improved without losing the characteristics of size, and low-temperature oxidation is possible, resulting in stable characteristics and high reliability.
The purpose is to provide a method for manufacturing FETs that can manufacture FETs with good reproducibility.
第２図ａ〜ｅは本発明の一実施例になるFET
の製造過程を示すためのその主要段階での断面図
で、まず、第２図ａに示すようにガラス基板１の
両面にプラズマCVDによつて窒化膜７を形成し、
ガラス基板１からナトリウムなどの可動イオンが
放出されるのを防ぐ。次に、第２図ｂに示すよう
にCrによるゲート電極２が写真製版工程を用い
て形成され、さらに、3000Åの厚さのシリコン窒
化膜によるゲート絶縁層３をCVD法で形成する。
つづいて、これを酸素プラズマにさらして、第２
図Ｃに示すようにゲート絶縁層３の表面約100Å
を酸化して酸化シリコン（SiO2）層８を形成す
る。これに第２図ｄに示すように、アモルフアス
シリコン層４並びにCr蒸着によるソース電極５
ａおよびドレイン電極５ｂをそれぞれ写真製版を
経て形成した後に第２図ｄに示すように全上面に
表面保護膜６を形成して、この実施例のFETは
完成する。 Figures 2a to 2e are FETs that are an embodiment of the present invention.
First, as shown in FIG. 2a, a nitride film 7 is formed on both sides of the glass substrate 1 by plasma CVD,
To prevent mobile ions such as sodium from being released from the glass substrate 1. Next, as shown in FIG. 2b, a gate electrode 2 made of Cr is formed using a photolithography process, and a gate insulating layer 3 made of a silicon nitride film with a thickness of 3000 Å is further formed by a CVD method.
Next, this was exposed to oxygen plasma and a second
As shown in Figure C, the surface of the gate insulating layer 3 is about 100 Å.
A silicon oxide (SiO 2 ) layer 8 is formed by oxidizing the silicon oxide (SiO 2 ). In addition, as shown in FIG. 2d, an amorphous silicon layer 4 and a source electrode 5 formed by Cr vapor deposition are added.
After forming the FET a and the drain electrode 5b by photolithography, a surface protective film 6 is formed on the entire upper surface as shown in FIG. 2d, thereby completing the FET of this embodiment.
このように、窒化膜からなるゲート絶縁層３の
表面を酸素プラズマにさらして酸化してSiO2層
８を形成したので、アモルフアスシリコン層４と
の界面に従来出現していた多くの準位はほとんど
が消滅し、キヤリアのトラツプ、放出現象は無視
してよい程度になる。従つて、シリコン窒化膜の
酸化にスパツタやCVD法を用いた場合に比し、
FETの特性は非常に安定し、再現性もよくなり、
長期のドリフトなどは問題なくなる。特に、レー
ザーなどのエネルギー線でアモルフアスシリコン
層４を再結晶化し多結晶層とした場合には特性向
上の度合は顕著で、非常に安定した良好な特性の
FETが得られる。 In this way, since the surface of the gate insulating layer 3 made of a nitride film was exposed to oxygen plasma and oxidized to form the SiO 2 layer 8, many levels that conventionally appeared at the interface with the amorphous silicon layer 4 were removed. Most of them disappear, and carrier trap and release phenomena become negligible. Therefore, compared to using sputtering or CVD methods to oxidize a silicon nitride film,
FET characteristics are very stable and reproducible,
Long-term drift will no longer be a problem. In particular, when the amorphous silicon layer 4 is recrystallized using energy beams such as a laser to form a polycrystalline layer, the degree of improvement in characteristics is remarkable, and very stable and good characteristics can be obtained.
FET is obtained.
第３図は本発明の他の実施例になる方法により
得られたFETを示す断面図で、ガラス基板１の
上にシリコン窒化膜９を形成し、その表面を酸素
プラズマにさらして酸化シリコン酸化膜１０を形
成し、この２層絶縁膜の上にフイールド酸化膜１
１で囲まれた領域にレーザー等で再結晶させたポ
リシリコンからなる活性領域１２とその両側にソ
ース領域１３およびドレイン領域１４とを形成
し、その上にゲート酸化膜１５で包まれたポリシ
リコンからなるゲート電極１６を形成し、更にそ
の上にフイールド酸化膜１１の上で含めて層間絶
縁膜１７を形成した後、その上に層間絶縁膜１７
およびゲート酸化膜１５のソース領域１３および
ドレイン領域１４の直上部分を貫通して、それぞ
れソース領域１３およびドレイン領域４に接続す
るソースアルミニウム配線１８およびドレインア
ルミニウム配線１９を形成したものである。この
実施例では上記実施例の効果に加えて、ガラス基
板１の上にシリコン窒化膜９とシリコン酸化膜１
０との二重層を形成したため、窒化膜９とシリコ
ン酸化膜１０との二重層を形成したため、窒化膜
のみを用いた場合に比して、いわゆるバツクチヤ
ネル（back channel）での電流が著しく減少し、
FETの特性の向上が達成できる。 FIG. 3 is a cross-sectional view showing an FET obtained by a method according to another embodiment of the present invention, in which a silicon nitride film 9 is formed on a glass substrate 1, and its surface is exposed to oxygen plasma to oxidize silicon oxide. A film 10 is formed, and a field oxide film 1 is formed on this two-layer insulating film.
An active region 12 made of polysilicon recrystallized by a laser or the like is formed in the region surrounded by 1, and a source region 13 and a drain region 14 are formed on both sides of the active region 12, and a polysilicon region surrounded by a gate oxide film 15 is formed on the active region 12. After forming a gate electrode 16 made of
A source aluminum wiring 18 and a drain aluminum wiring 19 are formed through the gate oxide film 15 directly above the source region 13 and drain region 14 to connect to the source region 13 and drain region 4, respectively. In addition to the effects of the above embodiments, this embodiment has a silicon nitride film 9 and a silicon oxide film 1 on the glass substrate 1.
Since a double layer of nitride film 9 and silicon oxide film 10 is formed, the current in the so-called back channel is significantly reduced compared to when only nitride film is used. ,
Improvements in FET characteristics can be achieved.
なお、上記各実施例ではシリコン窒化膜の表面
の酸化に酸素プラズマにさらす方法を示したが、
これは酸素雰囲気中で、シリコン窒化膜の表面に
紫外線、電子線、レーザ光などのエネルギー線を
照射する方法を用いてもよい。 In addition, in each of the above examples, a method of exposing the surface of the silicon nitride film to oxygen plasma was shown, but
This may be accomplished by irradiating the surface of the silicon nitride film with energy beams such as ultraviolet rays, electron beams, and laser beams in an oxygen atmosphere.
また、この発明の原理はキヤパシタの絶縁膜を
形成する場合にも適用することができ、この場合
も窒化膜のピンホールなとが酸化によつて埋まる
ので不良の発生が減少する等の効果がある。 Furthermore, the principle of the present invention can be applied to the formation of an insulating film for a capacitor, and in this case as well, pinholes in the nitride film are filled by oxidation, resulting in effects such as a reduction in the occurrence of defects. be.
以上説明したように、本発明によれば、基板上
に窒化シリコン膜を形成した後、該窒化シリコン
膜の表面を酸素プラズマにさらしてあるいは酸素
雰囲気中で該窒化シリコン膜表面にレーザ光を照
射して該窒化膜表面を酸化しその後形成された酸
化膜上にアモルフアスシリコンまたは多結晶シリ
コンからなる活性領域を形成するようにしたの
で、窒化膜の優れた特性を失うことなく活性領域
と絶縁層との界面特性をより向上できるとともも
に低温酸化が可能となり、特性の位定した信頼性
の高いFETを再現性よく製造できるという効果
がある。 As explained above, according to the present invention, after forming a silicon nitride film on a substrate, the surface of the silicon nitride film is exposed to oxygen plasma or the surface of the silicon nitride film is irradiated with laser light in an oxygen atmosphere. The surface of the nitride film is then oxidized, and then an active region made of amorphous silicon or polycrystalline silicon is formed on the oxide film, so that it can be insulated from the active region without losing the excellent properties of the nitride film. This has the effect that it is possible to further improve the interfacial characteristics with the layer, and also to enable low-temperature oxidation, making it possible to manufacture highly reliable FETs with well-defined characteristics with good reproducibility.
第１図ａは従来の薄膜構造のFETの構成を示
す縦断面図、第１図ｂはその平面図、第２図ａ〜
ｅは、本発明の一実施例になるFETの製造過程
を示すためのその主要段階での断面図、第３図は
本発明の他の実施例になる方法により得られた
FETを示す断面図である。
図において、１はガラス基板、２はゲート電
極、３は窒化シリコン膜、４はアモルフアスシリ
コン層、５ａはソース電極、５ｂはドレイン電
極、８は窒化シリコン膜３の表面を酸化した酸化
シリコン層、９は窒化シリコン膜、１０は窒化シ
リコン膜９の表面を酸化した酸化シリコン層、１
２は多結晶シリコン層（活性領域）、１３はソー
ス領域、１４はドレイン領域、１５はゲート絶縁
膜、１６はゲート電極である。なお、図中同一符
号は同一または相当部分を示す。
Figure 1a is a vertical cross-sectional view showing the configuration of a conventional thin film FET, Figure 1b is a plan view thereof, and Figures 2a--
e is a cross-sectional view at the main stages to show the manufacturing process of an FET that is an embodiment of the present invention, and Figure 3 is a cross-sectional view obtained by a method that is another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an FET. In the figure, 1 is a glass substrate, 2 is a gate electrode, 3 is a silicon nitride film, 4 is an amorphous silicon layer, 5a is a source electrode, 5b is a drain electrode, and 8 is a silicon oxide layer obtained by oxidizing the surface of the silicon nitride film 3. , 9 is a silicon nitride film, 10 is a silicon oxide layer obtained by oxidizing the surface of the silicon nitride film 9, 1
2 is a polycrystalline silicon layer (active region), 13 is a source region, 14 is a drain region, 15 is a gate insulating film, and 16 is a gate electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
を形成する工程、 上記窒化シリコン膜の表面を酸素プラズマにさ
らして、あるいは該窒化シリコン膜の表面に酸素
雰囲気中でエネルギー線を照射して酸化する工
程、 この表面を酸化して窒化シリコン膜上に活性領
域を構成するアモルフアスまたは多結晶シリコン
を形成する工程を備えたことを特徴とする電界効
果トランジスタの製造方法。[Claims] 1. A step of forming a silicon nitride film on a substrate by chemical vapor deposition, by exposing the surface of the silicon nitride film to oxygen plasma, or by exposing the surface of the silicon nitride film to an oxygen atmosphere. 1. A method for manufacturing a field effect transistor, comprising: oxidizing the surface by irradiating energy rays; and oxidizing the surface to form amorphous or polycrystalline silicon constituting an active region on a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3077282A JPS58147070A (en) | 1982-02-25 | 1982-02-25 | Field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3077282A JPS58147070A (en) | 1982-02-25 | 1982-02-25 | Field effect transistor and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58147070A JPS58147070A (en) | 1983-09-01 |
| JPH023308B2 true JPH023308B2 (en) | 1990-01-23 |
Family
ID=12312966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3077282A Granted JPS58147070A (en) | 1982-02-25 | 1982-02-25 | Field effect transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147070A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003086805A (en) * | 2001-09-07 | 2003-03-20 | Ricoh Co Ltd | Thin film transistor and electrical insulation film and method of manufacturing these |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60170972A (en) * | 1984-02-15 | 1985-09-04 | Sony Corp | Thin film semiconductor device |
| JPS61105863A (en) * | 1984-10-29 | 1986-05-23 | Seiko Epson Corp | Semiconductor image memory element |
| JPS6240773A (en) * | 1985-08-17 | 1987-02-21 | Sanyo Electric Co Ltd | Thin film transistor and manufacture thereof |
| JPS6319876A (en) * | 1986-07-11 | 1988-01-27 | Fuji Xerox Co Ltd | Thin film transistor device |
| JPS644070A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Thin film transistor and manufacture thereof |
| JPH03237790A (en) * | 1990-02-15 | 1991-10-23 | Shibaura Eng Works Co Ltd | Mounting method of electronic circuit parts |
| JPH0637317A (en) * | 1990-04-11 | 1994-02-10 | General Motors Corp <Gm> | Thin-film transistor and its manufacture |
| JPH07118527B2 (en) * | 1990-10-18 | 1995-12-18 | 富士ゼロックス株式会社 | Image sensor manufacturing method |
| US8344378B2 (en) * | 2009-06-26 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS567480A (en) * | 1979-06-29 | 1981-01-26 | Mitsubishi Electric Corp | Film transistor |
| JPS56111258A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Thin film semiconductor device |
| JPS577972A (en) * | 1980-06-19 | 1982-01-16 | Nec Corp | Insulated gate type thin film transistor |
-
1982
- 1982-02-25 JP JP3077282A patent/JPS58147070A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS567480A (en) * | 1979-06-29 | 1981-01-26 | Mitsubishi Electric Corp | Film transistor |
| JPS56111258A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Thin film semiconductor device |
| JPS577972A (en) * | 1980-06-19 | 1982-01-16 | Nec Corp | Insulated gate type thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003086805A (en) * | 2001-09-07 | 2003-03-20 | Ricoh Co Ltd | Thin film transistor and electrical insulation film and method of manufacturing these |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58147070A (en) | 1983-09-01 |
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