JPS61105863A - Semiconductor image memory element - Google Patents
Semiconductor image memory elementInfo
- Publication number
- JPS61105863A JPS61105863A JP59227505A JP22750584A JPS61105863A JP S61105863 A JPS61105863 A JP S61105863A JP 59227505 A JP59227505 A JP 59227505A JP 22750584 A JP22750584 A JP 22750584A JP S61105863 A JPS61105863 A JP S61105863A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- nonvolatile memory
- semiconductor
- intensity
- image storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims description 37
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052796 boron Inorganic materials 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract 3
- 239000010703 silicon Substances 0.000 claims abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体画像記憶素子の構造に関す２゜［従来
の技術〕
従来の半導体撮像素子として、ＭＯ８型撮像訃子がある
。２次元型ＭＯ８撮像素子の構成を第５図に示す。５１
は水平シフトレジスタであり、ＭＯＳスイッチ５３の一
つのゲートをオンしデータ線を選択し、５２は垂直シフ
トレジスタであり、ワード線の一つを選択し、画素部の
ＭＯＳスイッチ５６の一つを選択する。５７はフォトダ
イオードで、光信号を電気信号に変換する受光素子であ
る。また、５日はデータ読み出し線である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor image storage device. [Prior Art] As a conventional semiconductor imaging device, there is an MO8 type imaging device. FIG. 5 shows the configuration of a two-dimensional MO8 image sensor. 51
52 is a horizontal shift register that turns on one gate of the MOS switch 53 to select a data line, and 52 is a vertical shift register that selects one of the word lines and turns on one of the MOS switches 56 in the pixel section. select. 57 is a photodiode, which is a light receiving element that converts an optical signal into an electrical signal. Also, the 5th is a data read line.
フォトダイオード５７の原理は、まずフォトダイオード
を電源電圧まで充電する。ここで、光信号の強度に応じ
て発生した電荷がフォトダイオードの充電電圧を放電さ
せる。次にＭＯＳスイッチ５６がオン状態になれば、選
択されたフォトダイオードは再び電源電圧まで充電され
る。この充放電電流を共通のデータ読み出し線５８を通
して、負荷抵抗５９により、マトリックス状に配置され
た画素部の光情報を次々に出力信号として取り出し、画
像処理を行なう。The principle of the photodiode 57 is to first charge the photodiode to the power supply voltage. Here, the charge generated according to the intensity of the optical signal discharges the charging voltage of the photodiode. Next, when the MOS switch 56 is turned on, the selected photodiode is charged again to the power supply voltage. This charging/discharging current is passed through a common data readout line 58, and optical information of the pixel portions arranged in a matrix is successively extracted as an output signal by a load resistor 59, and image processing is performed.
このように前述の従来技術では２次元型ＭＯ８撮像素子
は、順次走査により、光情報を画素単位で次々と読み出
していくため、−画像において画素ごとに時間的なずれ
が生じる。一方、−画像情報の時間的なずれをなくすた
めにシフトレジスタの動作速度を速くすると、階調が取
りにくく雑音等の問題がでてくる。特に、画素密度が大
きくなったり、大面積化する場合、画像処理が大変むず
かしくなるという問題点があった。As described above, in the conventional technique described above, the two-dimensional MO8 image sensor sequentially reads out optical information pixel by pixel by sequential scanning, so that a temporal shift occurs from pixel to pixel in the image. On the other hand, if the operating speed of the shift register is increased in order to eliminate the time lag in image information, problems such as noise and the like will occur because it will be difficult to obtain gradations. In particular, when the pixel density increases or the area increases, there is a problem in that image processing becomes extremely difficult.
また、一画素につき、ＭＯＳスイッチ５６とフォトダイ
オード５７を必要とするため、フォトダイオードの占め
る面積を必要とする。Furthermore, since each pixel requires a MOS switch 56 and a photodiode 57, the area occupied by the photodiode is required.
また、ＭＯ８撮像素子自身で画素情報を記憶できないと
いう問題点もあった。Another problem was that the MO8 image sensor itself could not store pixel information.
そこで、本発明はこの様な問題点を解決するもので、そ
の目的とするところは、ＭＯ８撮像素子の画素部のＭＯ
Ｓスイッチの代わりに不揮発性メモリを用い、かつ、不
揮発性メモリのチャンネル部に光導電性の非晶質珪素を
用いることによって画像情報を読みこみ、直接不揮発性
メモリに記憶保持ができ、また、画像情報をすべての画
素に同時に読むことができ、時間的にずれのない高密度
大面積の画像処理を可能にする半導体画像記憶素子を提
供することにある。Therefore, the present invention is intended to solve such problems, and its purpose is to improve the MO of the pixel part of the MO8 image sensor.
By using a non-volatile memory instead of the S switch and using photoconductive amorphous silicon for the channel portion of the non-volatile memory, image information can be read and stored directly in the non-volatile memory, and An object of the present invention is to provide a semiconductor image storage element that can read image information to all pixels simultaneously and enables high-density, large-area image processing without temporal lag.
本発明の半導体画像記憶素子は、不揮発性メモリを用い
、かつ該不揮発性メモリのチャンネル部に導電性を有す
る非晶質半導体を用いたことを特徴とする。The semiconductor image storage device of the present invention is characterized in that it uses a nonvolatile memory and uses an amorphous semiconductor having conductivity in a channel portion of the nonvolatile memory.
本発明の上記の素子構成によれば、チャンネル部に入射
する光信号によりチャンネル部に光キャリアが発生し、
チャンネル部の抵抗が下がるため、ゲート・ソース間に
印加したある一定の書き込み電圧より、ゲート絶縁膜に
かかる電圧が光信号の強度に応じて変化するため、光信
号の強度に応じた電荷が半導体不揮発性メモリに記憶保
持されるため画像記憶ができる。According to the above element configuration of the present invention, optical carriers are generated in the channel portion by an optical signal incident on the channel portion,
Since the resistance of the channel part decreases, the voltage applied to the gate insulating film changes according to the intensity of the optical signal, rather than a certain writing voltage applied between the gate and source, so that the charge according to the intensity of the optical signal is transferred to the semiconductor. Images can be stored because they are stored in non-volatile memory.
また、上記の素子を用いて２次元型マ） ＩＪソックス
半導体画像装置に用いた場合、一画面の光情報をすべて
の画素に同時に記憶保持することができる。Further, when the above-mentioned element is used in a two-dimensional type IJ sock semiconductor image device, optical information of one screen can be stored and held in all pixels simultaneously.
第１図は、本発明の半導体画像記憶素子の一実施例であ
る。FIG. 1 shows an embodiment of the semiconductor image storage element of the present invention.
第１図において、ゲート絶縁膜として膜厚が４００＾の
非晶質窒化珪素１３と膜厚が２０Ｈの非晶質酸化珪素１
４の電荷捕獲準位を有する二層膜から成るＭＮＯＳ（金
属−窒化膜一酸化膜一半導体）型不揮発性メモリであり
、１２はゲート電極、１５はＭＮＯＳ型不揮発性メモリ
のチャンネル部となる光導電性のノンドープ又は極微量
のボロンドープｉ型（真性）非晶質珪素、１６はソース
・ドレイン部となるリンドープｎ型非晶質珪素、１７は
ソース俸ドレイン配線である。In FIG. 1, amorphous silicon nitride 13 with a film thickness of 400^ and amorphous silicon oxide 1 with a film thickness of 20H are used as gate insulating films.
This is an MNOS (metal-nitride-monoxide-semiconductor) type non-volatile memory consisting of a two-layer film having a charge trapping level of 4, where 12 is a gate electrode and 15 is a light beam which becomes the channel part of the MNOS type non-volatile memory. Conductive non-doped or extremely small amount of boron doped i-type (intrinsic) amorphous silicon, 16 is phosphorus-doped n-type amorphous silicon that becomes the source/drain portion, and 17 is source/drain wiring.
ここで、チャンネル部となるｉ型非晶質珪＋ｉ１５は、
光導電子素子として用いるため、非晶質酸化珪素１５と
ソース・ドレイン１６間の抵抗が、そこに入射する光強
度に応じて変化する。１１キ２図に、第１図の等何回路
を示す。Here, the i-type amorphous silicon + i15 that becomes the channel part is
Since it is used as a photoconductive element, the resistance between the amorphous silicon oxide 15 and the source/drain 16 changes depending on the intensity of light incident thereon. Figure 11-2 shows the equivalent circuit of Figure 1.
第２図を用いて、光情報の書き込み動作を説明する。ま
ず、ゲート２１．ソース２２間に、電子が、薄い酸化膜
をトンネルするのに適当な電圧（例えば＋３０ｖ）を印
加する。ここで、チャンネル部に光が入射することによ
り、光強度に応じた元キャリアが発生し、ゲート絶縁膜
にかかる電圧が変化し、Ｌ型非晶質珪素１５から電子が
、ゲート絶縁膜の電圧に応じた電荷量だけ、非晶質酸化
珪素膜１４をトンネルし、非晶質窒化珪素膜１３と非晶
質酸化珪素膜１４の界面や、非晶質窒化珪素膜１５の捕
獲準位に捕獲される。つまり、光強度に応じた情報を記
憶保持する。The optical information writing operation will be explained with reference to FIG. First, Gate 21. A suitable voltage (for example, +30V) is applied between the sources 22 to cause electrons to tunnel through the thin oxide film. Here, when light enters the channel part, original carriers are generated according to the light intensity, and the voltage applied to the gate insulating film changes, and electrons are transferred from the L-type amorphous silicon 15 to the voltage of the gate insulating film. The amount of charge corresponding to the amount of charge tunnels through the amorphous silicon oxide film 14 and is captured at the interface between the amorphous silicon nitride film 13 and the amorphous silicon oxide film 14 or at the trap level of the amorphous silicon nitride film 15. be done. In other words, information corresponding to the light intensity is stored and held.
第３図は、上記の半導体画像記憶素子を２次元の画像記
憶装置に応用した構成図である。３１は、Ｘドライバー
であり、データ線６４を選択し、３２はＸドライバーで
あり、ワード線５５を選択する。３６．３７は上記のチ
ャンネル部に光導電性素子となるｔ型非晶質珪素を用い
たＭＮＯＳ型不揮発性メモリである。６３は読み出し専
用のＭＯＳスイッチであり、６８は読み出し線である。FIG. 3 is a configuration diagram in which the above semiconductor image storage element is applied to a two-dimensional image storage device. 31 is an X driver that selects the data line 64; 32 is an X driver that selects the word line 55; 36 and 37 are MNOS type nonvolatile memories using T-type amorphous silicon, which serves as a photoconductive element, in the channel portion. 63 is a read-only MOS switch, and 68 is a read line.
この半導体画像記憶装置は、２次元の光情報を同時にす
べての画素に記憶することができる。これは、データ線
３４をすべて開放し、ワード線３５をすべて同時にオン
状態にしてすべての不揮発性メモリ３６のゲートに書き
込み電圧を印加することによって行なわれる。これによ
り、チャンネル部の光導電素子３７に入射する光信号の
強度に応じて３６のゲート絶縁膜にかかる電圧が変化し
、光信号の強度に応じた電荷が非晶質酸化珪素膜をトン
ネルし、絶縁膜中に記憶保持される。This semiconductor image storage device can simultaneously store two-dimensional optical information in all pixels. This is done by opening all the data lines 34, turning on all the word lines 35 at the same time, and applying a write voltage to the gates of all the nonvolatile memories 36. As a result, the voltage applied to the gate insulating film 36 changes depending on the intensity of the optical signal incident on the photoconductive element 37 in the channel portion, and the charge corresponding to the intensity of the optical signal tunnels through the amorphous silicon oxide film. , is stored and retained in the insulating film.
読み出しは、チャンネル部への入射光を一定にして、従
来の２次元型ＭＯ８撮像素子と同じようにマトリックス
状に配置された画像の一つをワード線３５とビット線３
４の組み合わせにより、ＭＯＳスイッチ３３を通して読
み出し録から出力信号を読み出し、ことにより行なわれ
、画像処理される。For readout, the incident light to the channel section is kept constant, and one of the images arranged in a matrix is connected to the word line 35 and the bit line 3 in the same way as in the conventional two-dimensional MO8 image sensor.
4, the output signal is read out from the readout record through the MOS switch 33, and image processing is performed.
ここで、３５のＭＯＳスイッチは、ＭＮＯＳ型不揮発性
メモリであり、このＭＮＯＳ型不揮発性メモリのしきい
値を適当に調節してＭＯＳスイッチとして代用している
。Here, the MOS switch 35 is an MNOS type nonvolatile memory, and the threshold value of this MNOS type nonvolatile memory is adjusted appropriately to be used as a MOS switch.
次に第４図に、本発明の半導体画像記憶素子の製造工程
を示す。まず絶縁物基板１１の上にゲート電極１２とし
てアルミ又は工Ｔｏ（酸化インジウムスズ）を形成し、
プラズマ気相成長法を用いて非晶質窒化珪素膜１３（４
００Ｘ）、非晶質酸化珪素膜１４（２０Ｘ）、ボロンを
０〜１１００ｐｐ 含むｔ型非晶質珪ｉ１ｓ、（１ｏｏ
ｏｏＸ）、リンを１００ ｐｐｍ 〜５％含むリンド
ープＮ型非晶質珪素１５（３０００Ｘ）を連続積層する
（（α））。読いて、チャンネル部となる龜型非晶質珪
素１５をリンドープ外型非晶質珪素１６と共にエツチン
グし、その上にｈｔ又は工Ｔ０１７を成膜する（（ｂ）
）。最後に、Ａｔ又は工ＴＯをエツチングし、ソース・
ドレイン配線１７を形成し、このｈｔ又は工Ｔｏをマス
クとして、ソース・ドレイン部を分離するために、リン
ドープｎ型非晶質珪素１８をエツチングする（（Ｃ））
。Next, FIG. 4 shows the manufacturing process of the semiconductor image storage element of the present invention. First, aluminum or To (indium tin oxide) is formed as a gate electrode 12 on an insulating substrate 11,
Amorphous silicon nitride film 13 (4
00
ooX), phosphorus-doped N-type amorphous silicon 15 (3000X) containing 100 ppm to 5% phosphorus is continuously laminated ((α)). After reading, the ferrule-shaped amorphous silicon 15 that will become the channel part is etched together with the phosphorus-doped outer-type amorphous silicon 16, and a film of HT or T017 is formed thereon ((b)
). Finally, etching At or TO, the source
A drain wiring 17 is formed, and the phosphorus-doped n-type amorphous silicon 18 is etched using this ht or etching TO as a mask to separate the source and drain parts ((C)).
.
〔効果〕
以上述べた様に本発明によれば、半導体不揮発性メモリ
のチャンネル部にｉ型非晶質珪素を用いたため、そのｔ
型非晶質珪素が光導電性を示すことから、この半導体不
揮発性メモリだけで、半導体画像記憶素子としての機能
を有するという効果を有する。すなわち、半導体不揮発
性メモリのチャンネル部に元情報が入射すると、光キャ
リアが発生し、チャンネル部の抵抗が光信号の強度に応
じて変化するため、半導体不揮発性メモリのゲーｔ・ソ
ース間に印加される適当な書き込み電圧により、ゲート
絶縁膜にかかる電圧が光信号の強度に応じて変化する。[Effect] As described above, according to the present invention, since i-type amorphous silicon is used in the channel portion of the semiconductor nonvolatile memory, its t
Since amorphous silicon exhibits photoconductivity, this semiconductor nonvolatile memory alone has the effect of functioning as a semiconductor image storage element. In other words, when original information enters the channel section of a semiconductor nonvolatile memory, optical carriers are generated and the resistance of the channel section changes depending on the intensity of the optical signal. The voltage applied to the gate insulating film varies depending on the intensity of the optical signal by applying an appropriate write voltage.
従って、元情報に応じた電荷が非晶質酸化膜をトンネル
して、非晶質酸化珪素膜と非晶質窒化珪素膜の界面又は
非晶質窒化珪素膜中の捕獲準位に捕獲され、光情報を記
憶保持するという特徴を有する。この記憶された光情報
は、不揮発性メモリを用いているため、電源が切れても
牛永久的に記憶されるという効果もある。Therefore, charges according to the original information tunnel through the amorphous oxide film and are captured at the interface between the amorphous silicon oxide film and the amorphous silicon nitride film or at the trap level in the amorphous silicon nitride film. It has the characteristic of storing and retaining optical information. Since this stored optical information uses non-volatile memory, it has the advantage that it is permanently stored even if the power is turned off.
また、本発明の半導体画像記憶素子は、半導体不揮発性
メモリのチャンネル部に光導電性を示すｔ型非晶質珪素
のみを用いただけなので、特別に光導電素子としての領
域を要しないため、単に電気信号のみを記憶する半導体
不揮発性メモリと楠本的には何も変わらず同等の面積で
よく、画素面積の小さい高精細度の半導体画像記憶装置
を作、５ことができる。また、プラズマ気相成長法を用
いているため、絶縁物基板としてガラス基板を用いれば
、安価で大面積の半導体画像記憶装置も作ることができ
るという効果も有する。Further, since the semiconductor image storage device of the present invention uses only T-type amorphous silicon exhibiting photoconductivity in the channel portion of the semiconductor nonvolatile memory, it does not require a special area as a photoconductive device. Kusumoto's method is no different from a semiconductor non-volatile memory that stores only electrical signals, and requires the same area, making it possible to create a high-definition semiconductor image storage device with a small pixel area. Furthermore, since a plasma vapor phase epitaxy method is used, an inexpensive, large-area semiconductor image storage device can be manufactured by using a glass substrate as an insulating substrate.
一方、第１図のように２次元型マトリックス状の画像記
憶装置は、−画像情報を同時にすべての画素に記憶でき
るため、走査して画像情報を記憶する必要がなく、画素
ごとによる時間的なずれが生じないという効果を有する
。On the other hand, a two-dimensional matrix image storage device as shown in Figure 1 can store image information in all pixels at the same time, so there is no need to scan and store image information, and there is no need to store image information by scanning. This has the effect that no misalignment occurs.
また、ＭＯＳスイッチ等をしきい値を制御したＭＮＯＳ
型不揮発性メモリで代用すれば、フォト工程が第４図に
示すように６エ程でよく、製造工程が非常にＰＭ単にな
り安価な半導体画像記憶装置を製造することができると
いう効果も有する。In addition, MNOS with controlled threshold values for MOS switches, etc.
If a type non-volatile memory is used instead, the photo process only needs to be about 6 steps as shown in FIG. 4, and the manufacturing process becomes very simple PM, which also has the effect of making it possible to manufacture an inexpensive semiconductor image storage device.
第１図は本発明の半導体画像記憶素子の一実施例を示す
構造図であり、第２図は第１図の等価回路図である。第
３図は、本発明の半導体画像記憶素子を用いた２次元型
半導体画像記憶装置を示す図である。第４図（α）〜（
Ｃ）は本発明の半導体画像記憶素子の製造工程を示す図
。第５図は従来の２次元型ＭＯ３撮像素子の構成を示す
図。
１１・・・・・・絶縁物基板
１２・・・・・・ゲート電極
１３・・・・・・非晶質窒化珪素
１４・・・・・・非晶質酸化珪素
１５・・・・・・非晶質珪素
１６・・・・・・ｎ型非晶質珪素
１７・・・・・・ｐ、Ｌ又は工ＴＯ配線２１・・・・・
・ゲート
２２・・・・・・ソース
２３・・・・・・ドレイン
３１・・・・・・Ｘドライバー
３２・・・・・・Ｘドライバー
６３・・・・・・ＭＯＳスイッチ
３４・・・・・・データ線
３５・・・・・・ワード線
３６・・・・・・ＭＮＯＳ型不揮発性メモリ３７・・・
・・・光導電素子
３８・・・・・・読み出し線
５１・・・・・・水平シフトレジスタ
５２・・・・・・垂直シフトレジスタ
５６・・・・・・ＭＯＳスイッチ
５４・・・・・・データ線
５５・・・・・・ワード線
５６・・・・・・ＭＯＳスイッチ
５７・・・・・・フォトダイオード
５８・・・・・・読み出し線
５９・・・・・・負荷抵抗
以 上FIG. 1 is a structural diagram showing an embodiment of the semiconductor image storage element of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1. FIG. 3 is a diagram showing a two-dimensional semiconductor image storage device using the semiconductor image storage element of the present invention. Figure 4 (α) - (
C) is a diagram showing the manufacturing process of the semiconductor image storage element of the present invention. FIG. 5 is a diagram showing the configuration of a conventional two-dimensional MO3 image sensor. 11...Insulator substrate 12...Gate electrode 13...Amorphous silicon nitride 14...Amorphous silicon oxide 15... Amorphous silicon 16...N-type amorphous silicon 17...P, L or engineering TO wiring 21...
・Gate 22...Source 23...Drain 31...X driver 32...X driver 63...MOS switch 34... ...Data line 35...Word line 36...MNOS type nonvolatile memory 37...
... Photoconductive element 38 ... Readout line 51 ... Horizontal shift register 52 ... Vertical shift register 56 ... MOS switch 54 ...・Data line 55...Word line 56...MOS switch 57...Photodiode 58...Readout line 59...Load resistance or more
Claims (5)
性メモリのチャンネル部に光導電性を有する非晶質珪素
を用いたことを特徴とする半導体画像記憶素子。(1) A semiconductor image storage element in a semiconductor nonvolatile memory, characterized in that amorphous silicon having photoconductivity is used in a channel portion of the semiconductor nonvolatile memory.
ｍ含む該非晶質珪素を用いたことを特徴とする特許請求
の範囲第１項記載の半導体画像記憶素子。(2) 0 to 100 pp of boron as the amorphous silicon
The semiconductor image storage device according to claim 1, characterized in that the amorphous silicon containing m is used.
を電荷捕獲準位を有する酸化珪素膜と窒化珪素膜の二層
膜とするＭＮＯＳ（金属−窒化珪素−酸化珪素−半導体
）型不揮発性メモリを用いたことを特徴とする特許請求
の範囲第１項記載の半導体画像記憶素子。(3) The semiconductor nonvolatile memory is an MNOS (metal-silicon nitride-silicon oxide-semiconductor) type nonvolatile memory in which the gate insulating film is a two-layer film of a silicon oxide film and a silicon nitride film having a charge trapping level. A semiconductor image storage device according to claim 1, wherein the semiconductor image storage device is used.
て、該酸化珪素膜の厚さが７５Å〜８０Åである非晶質
酸化珪素膜であることを特徴とする特許請求の範囲第１
項記載の半導体画像記憶素子。(4) The silicon oxide film of the MNOS type nonvolatile memory is an amorphous silicon oxide film having a thickness of 75 Å to 80 Å.
2. The semiconductor image storage device described in 2.
て、該窒化珪素膜の厚さが１００Å〜８００Åである非
晶質窒化珪素膜であることを特徴とする特許請求の範囲
第１項記載の半導体画像記憶素子。(5) The silicon nitride film of the MNOS type nonvolatile memory is an amorphous silicon nitride film having a thickness of 100 Å to 800 Å. Semiconductor image storage element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227505A JPS61105863A (en) | 1984-10-29 | 1984-10-29 | Semiconductor image memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227505A JPS61105863A (en) | 1984-10-29 | 1984-10-29 | Semiconductor image memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61105863A true JPS61105863A (en) | 1986-05-23 |
Family
ID=16861945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59227505A Pending JPS61105863A (en) | 1984-10-29 | 1984-10-29 | Semiconductor image memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61105863A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270567A (en) * | 1989-09-06 | 1993-12-14 | Casio Computer Co., Ltd. | Thin film transistors without capacitances between electrodes thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325635A (en) * | 1976-08-21 | 1978-03-09 | Sumitomo Metal Ind | Apparatus for fly prevention of slag particles |
| JPS58147070A (en) * | 1982-02-25 | 1983-09-01 | Mitsubishi Electric Corp | Field effect transistor and manufacture thereof |
-
1984
- 1984-10-29 JP JP59227505A patent/JPS61105863A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325635A (en) * | 1976-08-21 | 1978-03-09 | Sumitomo Metal Ind | Apparatus for fly prevention of slag particles |
| JPS58147070A (en) * | 1982-02-25 | 1983-09-01 | Mitsubishi Electric Corp | Field effect transistor and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270567A (en) * | 1989-09-06 | 1993-12-14 | Casio Computer Co., Ltd. | Thin film transistors without capacitances between electrodes thereof |
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