CN111554700B - Imaging array based on composite dielectric gate structure and exposure and reading methods thereof - Google Patents
Imaging array based on composite dielectric gate structure and exposure and reading methods thereof Download PDFInfo
- Publication number
- CN111554700B CN111554700B CN202010401623.5A CN202010401623A CN111554700B CN 111554700 B CN111554700 B CN 111554700B CN 202010401623 A CN202010401623 A CN 202010401623A CN 111554700 B CN111554700 B CN 111554700B
- Authority
- CN
- China
- Prior art keywords
- row
- pixel units
- pixel
- column
- columns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000002131 composite material Substances 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 10
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000003860 storage Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000001444 catalytic combustion detection Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
Abstract
The invention provides an imaging array based on a composite dielectric gate structure and exposure and reading methods thereof. The imaging array comprises pixel units with composite dielectric grid structures, wherein the source electrode and the drain electrode of each pixel unit are symmetrical, a plurality of units are connected in series to form a row, the drain electrode or the source electrode is shared between adjacent units in the same row, the drain electrodes or the source electrodes of the units in the rows are respectively connected with the drain electrodes or the source electrodes in the corresponding positions of other rows through N-type injection regions in a longitudinal mode to form a plurality of columns, and in the same column, the N-type injection regions in a plurality of rows at intervals are connected to a column of metal layer wires through ohmic contacts; one end of a column of metal layer is provided with a selection switch transistor; the control gates of each row of cells are connected in a single block with lateral extension, and in the same row, the control gates of cells separated by columns are connected to a row of metal layer word lines using ohmic contacts. The invention can effectively further reduce the pixel period size and improve the imaging resolution.
Description
Technical Field
The invention relates to a pixel unit with a composite dielectric gate structure, in particular to a Virtual Group (VG) array architecture formed by the pixel units with the composite dielectric gate structure and an exposure and reading method thereof.
Background
Image sensors are very widely used in today's society, such as in the fields of mobile phones, digital cameras, various video cameras, and national defense detection. The main imaging detectors developed at present are of two types, namely CCD and CMOS-APS, wherein the basic structure of the CCD is that a series of MOS capacitors are connected in series, and the generation and the change of potential wells on the surface of a semiconductor are controlled through the voltage pulse time sequence on the capacitors, so that the storage, the transfer and the readout of photo-generated charge signals are realized; each pixel of the CMOS-APS is composed of a diode and a plurality of transistors, and the change condition before and after exposure is read to obtain an optical signal. CMOS-APS have become the dominant market in recent years due to certain advantages, and CCD production has very high process requirements and less than ideal yields and costs. At present, both CCDs and CMOS are striving to further reduce the pixel size to increase the resolution, and the CCD is difficult to further reduce the pixel size due to the effect of fringe electric fields and the like. And each pixel of the CMOS-APS is composed of a plurality of transistors and a light sensing diode, so that the light sensing area of each pixel occupies only small surface area of the pixel, and the sensitivity and resolution are relatively small. In addition, CMOS-APS includes a plurality of transistors for performing address strobe operations (a typical pixel unit includes three transistors), which determines that the pixel size reduction is greatly limited.
In order to obtain an imaging device with a simple structure, a mature process and a higher resolution, the prior patent US6784933B1 proposes a structure using one non-volatile floating gate memory transistor and two selection transistors as pixel units, which is not only simple but also compatible with the standard process, but at least three transistors are included in one pixel of the structure. In order to reduce the pixel size to a large extent, patent WO2010094233 proposes a structure using a floating gate transistor as a pixel unit to effectively increase the imaging density, and further proposes a reliable exposure imaging method for the pixel unit structure in patent CN103165628 a. In order to realize the readout of the array device, the CMOS-APS usually adopts X-Y cross-addressing, but this array architecture needs more leads, the pixel arrangement is not compact enough, in patent US6784933B1, the floating gate transistor pixel adopts NOR architecture, and an electrode lead is needed between every two adjacent pixels, which also increases the pixel size.
Disclosure of Invention
The purpose of the invention is that: based on the pixel unit of the composite dielectric gate structure, an imaging array of a Virtual Group (VG) structure is provided, so that the pixel period size can be effectively further reduced, and the imaging resolution is improved. It is another object of the present invention to provide a method of exposing and reading the imaging array.
The imaging array adopts the technical scheme that:
the imaging array based on the composite dielectric gate structure consists of a plurality of pixel units, the pixel units adopt the composite dielectric gate structure, the source electrode and the drain electrode of each pixel unit are symmetrically arranged, a plurality of pixel units are mutually connected in series to form a row, the drain electrode or the source electrode is shared between adjacent pixel units in the same row, and the drain electrodes or the source electrodes of the pixel units in a plurality of rows are longitudinally connected with the drain electrodes or the source electrodes in the corresponding positions of other rows through N-type injection regions respectively to form a plurality of columns; in the same column, N-type injection regions separated by a plurality of rows are connected to a column of metal layer wires by using ohmic contact, so that pixel units in the same column are connected in parallel; one end of a column of metal layer is provided with a selection switch transistor, and the switch transistors of the odd columns and the even columns are positioned at different ends; the control gates of each row of pixel cells are connected in a laterally extending fashion as a unit, and in the same row, the control gates of pixel cells separated by columns are connected to a row of metal layer word lines using ohmic contacts.
Further, the substrate of the imaging array is a common p-type substrate formed by implantation.
Further, the number of rows of pixel units in the same column are 8 to 64 rows.
Further, a negative bias pulse Vb is applied to the substrate; in the exposure process, the grid connection voltage Von of all the selective switch transistors is ensured to be started; the other end of the selective switch transistor which is not connected with the array is added with a forward voltage pulse Vp; the control gate is applied with a zero forward bias pulse Vg.
The invention discloses an exposure method of an imaging array based on a composite dielectric gate structure, which comprises the following steps: applying a negative bias pulse Vb to the substrate; the gate of the selection switch transistor connected with the odd columns or the even columns is connected with the voltage Von in the exposure process, so that the start is ensured; the gate of the selection switch transistor connected with the even number column or the odd number column is connected with the voltage Voff, so that the turn-off is ensured; the other end of the odd-numbered or even-numbered selective switch transistor which is not connected with the array is added with a forward voltage pulse Vp; the control gate is applied with a zero forward bias pulse Vg.
The invention relates to another imaging array reading method based on a composite dielectric gate structure, which specifically comprises the following steps: the substrate is grounded, and positive bias voltage Vgr is applied to a word line of a row where a pixel unit to be read is located; the grid electrodes of two selection tubes on two bit lines directly connected with the pixel units to be read are turned on by positive voltage Von, and two ends of the two selection tubes which are not connected with the array are grounded by one and one is added with positive voltage Vd; all other selection tube gates are turned off by the voltage Voff; the magnitude of the current in the bit line to which the selected pixel cell is connected is read, and the magnitude of the optical signal is determined by the magnitude of the current.
The beneficial effects of the invention are as follows:
(1) The pixel unit adopts a composite dielectric gate structure, and one transistor is very simple as one pixel structure, thereby being beneficial to improving the resolution.
(2) According to the pixel structure and imaging characteristics, transversely adjacent pixels share a source region or a drain region, the source region or the drain region is longitudinally connected through an n+ injection region, the n+ injection region is connected to the same layer of metal through metal contact every other (8-64) rows to ensure the equipotential of the n+ region, so that parallel connection of pixel units is realized, and each pixel unit does not need to have metal contact of a source electrode or a drain electrode; according to the array layout structure, a control gate is not arranged above a non-channel non-n+ region, and the problem of inter-pixel conduction crosstalk does not exist, so that inter-pixel isolation in modes such as STI and the like is not needed.
(3) The invention can effectively realize the tight arrangement of pixels without changing the pixel unit structure, and can greatly improve the pixel density of an imaging array and the resolution.
(4) The invention provides an exposure method suitable for the imaging array, which can control global exposure imaging of the imaging array by adjusting voltage and has the characteristics of no dark current interference and high imaging speed.
(5) The invention provides a reading method suitable for the imaging array, which effectively avoids fixed pattern noise caused by different metal line resistances connected in series by pixels at different positions of the array by controlling the same-size series resistance of all pixel units during reading.
Drawings
FIG. 1 is a schematic diagram of a composite dielectric gate photosensitive detector according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a composite dielectric gate photosensitive detector according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an imaging array based on a pixel unit with a composite dielectric gate structure according to the present invention;
FIG. 4 is a layout of an imaging array based on a pixel unit with a composite dielectric gate structure;
FIG. 5 is a schematic view of an imaging array exposure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an array reading of an image according to an embodiment of the invention.
Detailed Description
The pixel unit structure related to the imaging array of the present embodiment, as shown in fig. 1, is a composite dielectric gate structure, including: a bottom insulating medium 6, a charge storage layer 5, a top insulating medium 4 and a control gate 3 are sequentially arranged right above the substrate 1 of the P-type semiconductor substrate 1; the P-type semiconductor substrate 1 is doped by ion implantation to form a high-concentration N-type source region 7 and a high-concentration N-type drain region 2 on both sides close to the stacked dielectric. The charge storage layer 5 is polysilicon, si3N4 or other electron conductor or semiconductor; the control gate 3 is a polysilicon, metal or other transparent conductive electrode, and at least one of the control gate surface or the substrate layer is a window transparent or semitransparent to the wavelength of detection by the detector. The top insulating medium 4 and the bottom insulating medium 6 can effectively isolate the charge storage region, so that charges are limited in the charge storage layer 5 to realize a storage function, and the top insulating medium 4 is generally a broadband semiconductor so as to ensure that electrons cannot enter the control gate 3 after crossing a potential barrier from a substrate and entering the storage layer. The top dielectric material may be silicon oxide/silicon nitride/silicon oxide, silicon oxide/aluminum oxide/silicon oxide, aluminum oxide or other high dielectric constant dielectric materials. The underlying dielectric material may be silicon oxide or other high dielectric constant dielectric. A specific description of this composite dielectric gate structure can be found in patent WO2010/094233. Fig. 2 is a circuit diagram showing a pixel unit structure.
The basic architecture of the imaging array of this embodiment is shown in fig. 3, where N is an even number, the P-type semiconductor substrate 1 is a P-type substrate formed by implantation, the drain electrode 2 or the source electrode 7 shared between adjacent pixel units, a plurality of pixel units are connected in series to form a row, the drain electrode or the source electrode is shared between adjacent pixel units in the same row, and the drain electrode or the source electrode of each pixel unit in each row is longitudinally connected with the drain electrode or the source electrode in the corresponding position of other rows through the N-type implantation region to form a plurality of columns. In the same column, connecting N-type injection regions separated by a plurality of rows to a column of metal layer Bit Lines (BL) by using ohmic contact so that pixel units in the same column are mutually connected in parallel; for example, in a first column, the N-type implant regions between row 1, row 33, row 32, and row 65, row 64 are connected to the same metal layer using ohmic contacts, the remaining columns are similarly connected to respective metal layers, and the metal layers of each column are insulated from each other. A selection switch transistor (BLSel) is arranged at one end of a column of metal layer Bit Lines (BL), and the switch transistors of the odd columns and the even columns are positioned at different ends. The control gates 3 of each row of pixel units are connected in a transversely extending manner as a whole, and in the same row, the control gates of pixel units separated by a plurality of columns are connected to one metal layer Word Line (WL) by using ohmic contact, and the gates of one row of pixels are controlled simultaneously; for example, in the first row, the control gates of the 1 st, 321 st, 641 st pixel units are connected to the same metal layer using ohmic contacts, and the other rows are similarly connected to respective metal layers, and the metal layers of the rows are insulated from each other. The number of rows of the pixel array in which the N-type implant regions are connected to the metal contacts of the metal layer may be 8-64. The array adopts the common source and drain of the pixels and uses the N+ injection region to connect the source and drain of the parallel pixels, the source and drain of each pixel do not need metal contact, the array is simple, and the pixel density is higher. Fig. 4 is a layout of an imaging array.
As shown in fig. 5, a negative bias pulse Vb is applied to the substrate during the exposure of the array; one end or the other end of each pixel unit of one column is provided with a selection switch transistor, all selection tube grids are added with Von in the exposure process, the other end of each selection tube, which is not connected with the array, is added with a forward voltage pulse Vp, or the selection tube grids connected with the odd columns in the exposure process are added with Von, the selection tube grids connected with the even columns are added with Voff, the selection tube of the odd columns is turned off, the other end of each selection tube, which is not connected with the array, is added with a forward voltage pulse Vp, or the selection tube grids connected with the even columns in the exposure process are added with Von, the selection tube grids connected with the odd columns are turned on, the selection tube grids connected with the odd columns are added with Voff, the other end of each selection tube, which is not connected with the array, is added with a forward voltage pulse Vp; the control gate 3 applies a forward bias pulse Vg.
As shown in fig. 6, when reading a selected pixel cell, the substrate is grounded, and a positive bias Vgr is applied to the word line of the row where the pixel cell to be read is located; the gates of the two select transistors on the two BL directly connected to the pixel cell to be read are turned on with positive voltage Von and the two ends of the two select transistors not connected to the array are grounded one by one with positive voltage Vd. All remaining select gates are turned off with Voff. The magnitude of the current in the BL to which the selected pixel cell is connected is read, and the magnitude of the optical signal is determined by the magnitude of the current.
The purpose of the BL select tubes of the odd-even columns at the different ends of the BL is that the resistance of the metal line in series with the source and drain of the pixel is equal to the resistance of a column of metal, regardless of which pixel in the imaging array is read. Thus, fixed pattern noise caused by different resistances of metal lines connected in series between pixels at different positions of the array can be avoided to a certain extent during reading.
Preferably, vb is-20 to 0V, vp is 0 to 10V, vg is 0 to 20V, von is-5 to 5V, voff is-5 to 5V, vgr is 0 to 10V, and Vd is 0 to 2V.
Claims (6)
1. The imaging array is composed of a plurality of pixel units, the pixel units are of a composite dielectric gate structure, the source electrode and the drain electrode of each pixel unit are symmetrically arranged, a plurality of pixel units are mutually connected in series to form a row, the drain electrode or the source electrode is shared between adjacent pixel units in the same row, and the drain electrode or the source electrode of each pixel unit in each row is longitudinally connected with the drain electrode or the source electrode in the corresponding position of other rows through an N-type injection region to form a plurality of columns; in the same column, N-type injection regions separated by a plurality of rows are connected to a column of metal layer wires by using ohmic contact, so that pixel units in the same column are connected in parallel; one end of a column of metal layer is provided with a selection switch transistor, and the switch transistors of the odd columns and the even columns are positioned at different ends; the control grid electrodes of each row of pixel units are transversely extended and connected into a whole, and in the same row, the control grid electrodes of pixel units separated by a plurality of columns are connected to a row of metal layer word lines by using ohmic contacts; the method is characterized by comprising the following steps: applying a negative bias pulse Vb to the substrate; one end or the other end of each pixel unit in a column is provided with a selection switch transistor, and the grid of all the selection switch transistors is connected with voltage Von in the exposure process, so that the starting is ensured; the other end of the selective switch transistor which is not connected with the array is added with a forward voltage pulse Vp; the control gate is applied with a zero forward bias pulse Vg.
2. The exposure method according to claim 1, wherein the negative bias pulse Vb is-20 to 0V, the positive voltage pulse Vp is 0 to 10V, the zero positive bias pulse Vg is 0 to 20V, and the voltage Von is-5 to 5V.
3. The imaging array is composed of a plurality of pixel units, the pixel units are of a composite dielectric gate structure, the source electrode and the drain electrode of each pixel unit are symmetrically arranged, a plurality of pixel units are mutually connected in series to form a row, the drain electrode or the source electrode is shared between adjacent pixel units in the same row, and the drain electrode or the source electrode of each pixel unit in each row is longitudinally connected with the drain electrode or the source electrode in the corresponding position of other rows through an N-type injection region to form a plurality of columns; in the same column, N-type injection regions separated by a plurality of rows are connected to a column of metal layer wires by using ohmic contact, so that pixel units in the same column are connected in parallel; one end of a column of metal layer is provided with a selection switch transistor, and the switch transistors of the odd columns and the even columns are positioned at different ends; the control grid electrodes of each row of pixel units are transversely extended and connected into a whole, and in the same row, the control grid electrodes of pixel units separated by a plurality of columns are connected to a row of metal layer word lines by using ohmic contacts; the method is characterized by comprising the following steps: applying a negative bias pulse Vb to the substrate; one end or the other end of the pixel unit of one column is provided with a selection switch transistor, and the grid of the selection switch transistor connected with the odd columns or the even columns is connected with voltage Von in the exposure process, so that the starting is ensured; the gate of the selection switch transistor connected with the even number column or the odd number column is connected with the voltage Voff, so that the turn-off is ensured; the other end of the odd-numbered or even-numbered selective switch transistor which is not connected with the array is added with a forward voltage pulse Vp; the control gate is applied with a zero forward bias pulse Vg.
4. The exposure method according to claim 3, wherein the negative bias pulse Vb is-20 to 0V, the positive bias pulse Vp is 0 to 10V, the zero positive bias pulse Vg is 0 to 20V, the voltage Von is-5 to 5V, and the voltage Voff is-5 to 5V.
5. The exposure method according to any one of claims 1 to 4, wherein, when reading a selected pixel cell, the substrate is grounded, and a positive bias Vgr is applied to a word line of a row in which the pixel cell to be read is located; the grid electrodes of two selection tubes on two bit lines directly connected with the pixel units to be read are turned on by positive voltage Von, and two ends of the two selection tubes which are not connected with the array are grounded by one and one is added with positive voltage Vd; all other selection tube gates are turned off by the voltage Voff; the magnitude of the current in the bit line to which the selected pixel cell is connected is read, and the magnitude of the optical signal is determined by the magnitude of the current.
6. The exposure method according to claim 5, wherein the voltage Von is-5 to 5V, the voltage Voff is-5 to 5V, the positive bias Vgr is 0 to 10V, and the positive voltage Vd is 0 to 2V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010401623.5A CN111554700B (en) | 2020-05-13 | 2020-05-13 | Imaging array based on composite dielectric gate structure and exposure and reading methods thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010401623.5A CN111554700B (en) | 2020-05-13 | 2020-05-13 | Imaging array based on composite dielectric gate structure and exposure and reading methods thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111554700A CN111554700A (en) | 2020-08-18 |
| CN111554700B true CN111554700B (en) | 2023-09-12 |
Family
ID=72008112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010401623.5A Active CN111554700B (en) | 2020-05-13 | 2020-05-13 | Imaging array based on composite dielectric gate structure and exposure and reading methods thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111554700B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538375A (en) * | 2003-04-16 | 2004-10-20 | ������������ʽ���� | Driving method of electrooptical device, electrooptical device and electronic equipment |
| CN101807547A (en) * | 2009-02-18 | 2010-08-18 | 南京大学 | Photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector |
| CN103137642A (en) * | 2013-03-21 | 2013-06-05 | 北京思比科微电子技术股份有限公司 | Pixel unit of complementary metal oxide semiconductor (CMOS) image sensor and CMOS image sensor |
-
2020
- 2020-05-13 CN CN202010401623.5A patent/CN111554700B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538375A (en) * | 2003-04-16 | 2004-10-20 | ������������ʽ���� | Driving method of electrooptical device, electrooptical device and electronic equipment |
| CN101807547A (en) * | 2009-02-18 | 2010-08-18 | 南京大学 | Photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector |
| CN103137642A (en) * | 2013-03-21 | 2013-06-05 | 北京思比科微电子技术股份有限公司 | Pixel unit of complementary metal oxide semiconductor (CMOS) image sensor and CMOS image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111554700A (en) | 2020-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6878918B2 (en) | APS pixel with reset noise suppression and programmable binning capability | |
| US8698932B2 (en) | Solid-state image pickup apparatus and camera | |
| CN107658321B (en) | Dual-device photosensitive detection unit based on composite dielectric grid, detector and method thereof | |
| JPS60206063A (en) | Solid-state image pickup element and solid-state image pickup device | |
| US10741593B1 (en) | Vertical transfer gate storage for a global shutter in an image sensor | |
| CN100555648C (en) | Cmos image sensor | |
| JPS62265759A (en) | Solid state image pickup element | |
| EP1115245B1 (en) | Solid state imaging device and driving method thereof | |
| CN108666336B (en) | UTBB photoelectric detector array and working method thereof | |
| JPS59108476A (en) | Two-dimensional solid-state image pickup device and its readout method | |
| KR100265269B1 (en) | Solid state image sensing device having vertical overflow drain and resistive gate charge transfer element and method of control the same | |
| US4995061A (en) | Two-phase CCD imager cell for TV interlace operation | |
| US11012645B2 (en) | Solid-state image sensor | |
| US5504526A (en) | Solid-state image sensing device with storage-diode potential controller | |
| CN111554700B (en) | Imaging array based on composite dielectric gate structure and exposure and reading methods thereof | |
| CN103227184B (en) | Based on imaging array and the exposing operation method thereof of composite dielectric gate structure-pixel unit | |
| US5134087A (en) | Fabricating a two-phase CCD imager cell for TV interlace operation | |
| JPH06120262A (en) | Charge transfer device | |
| JP3718103B2 (en) | Solid-state imaging device, driving method thereof, and camera using the same | |
| CN111554699A (en) | Photosensitive detection unit based on composite dielectric gate structure, detector and method thereof | |
| CN103066097A (en) | High-sensitivity solid-state color image sensor | |
| JP3060649B2 (en) | Semiconductor device and driving method thereof | |
| US7642579B2 (en) | Image sensor comprising pixels with one transistor | |
| JP6967716B2 (en) | Photodetector and image pickup device | |
| KR960015532B1 (en) | Solid state image pick-up device and manufacturing and driving method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |