CN101807547A - Photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector - Google Patents
Photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector Download PDFInfo
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Abstract
The invention relates to an arrangement method of a photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector. Each unit detector has a structure that N-shaped semiconductor regions are respectively arranged at both upper sides of a P-shaped semiconductor material of a substrate, two insulated dielectric material layers and a control grid electrode are respectively arranged over the substrate, a photoelectron storage layer is arranged between the two insulated dielectric material layers, the second insulated dielectric in contact with the control grid is made of a material preventing charges stored in the photoelectron storage layer from flowing into the grid electrode, a source electrode and a drain electrode are in suspended structures when photoelectrons are collected and stored to the photoelectron storage layer, the first insulated dielectric is a bottom dielectric and adopts silica, SiON or other dielectric materials with high dielectric constants, the second insulated dielectric layer is made from a top dielectric and adopts silica/silicon nitride/silica, silica, alumina or other dielectric materials with high dielectric constants, and the substrate layer or the grid electrode surface is provided with at least one transparent or semi-transparent window for detecting the wavelength of the detector.
Description
One, technical field
The present invention relates to the imaging detection device, especially infrared, visible light wave range is to structure, working mechanism, setting and the method for operation of the imaging detection device of ultraviolet band.
Two, background technology
The imaging detection device of development mainly is CCD and CMOS-APS at present, CCD device basic functional principle is relevant with the Physical Mechanism of Metal-oxide-silicon (MOS) electric capacity, the basic composition unit of CCD is the mos capacitance device, and its course of work mainly is generation, storage, transfer and the detection of signal charge.CCD is the device of signal being stored, being shifted with the form of charge packet, and its outstanding characteristic is to be signal with the electric charge, is the device of signal with the curtage and be different from other.During CCD work, produce and control the variation of semiconductor potential well, and then realize the storage and the transfer of electric charge by clock pulse voltage.CMOS-APS is as Chinese patent CN1774814 etc.
Typical visible light wave range image device CCD specification and pixel size:
maximum specification 10k x 10k (DALSA)
minimum pixel 2.4 microns (e2V) can't dwindle
well depth～1000e-/μ m
2
Typical case's CMOS-APS pixel specification (CMOS-APS imaging pixel unit has four big functions, photoelectron is collected and stored, amplifies, resets, addressing):
maximum specification 4k x 4k (0.18 micron technology, Raytheon etc.)
2.8 microns (0.25 micron technology Panasonic) is difficult to dwindle the minimum pixel
well depth 3000e-/micron μ m
2(18 microns x18 microns of Micron pixel)
CCD and CMOS-APS comprehensively are compared as follows table:
| ??CCD | ??CMOS--APS | |
| Leakage current | Very good＜1nA/cm2 | Bad＞50nA/cm2 |
| Duty ratio (Fill Factor) | Very good～100% | Bad＜60% |
| Technological requirement with | Very high | Generally |
| Rate of finished products | Rate of finished products is low | The rate of finished products height |
| Compatibility with CMOS technology | Incompatible | Compatible |
The limitation of CCD and CMOS-APS: CCD and CMOS-APS be current from scientific instrument to the family expenses image documentation equipment the image-forming component of extensive use, but existing two kinds of image-forming components all have its unsurmountable shortcoming.CCD be in essence be parallel to each other can the directional transmissions electric charge a large amount of mos capacitances of series connection mutually, its limitation shows:
1) image taking speed is difficult to improve: need physical property ground dislocation charge in the CCD imaging process, therefore, its image taking speed is difficult to improve.
2) rate of finished products is low: because its mos capacitance framework of connecting mutually and the needs of transmission charge, in CCD pixel with delegation's series connection, any one mos capacitance lost efficacy or cisco unity malfunction all can influence the normal transmission of electric charge at this electric capacity, thereby caused coming in this row CCD pixel this electric capacity pixel cisco unity malfunction afterwards.Be usually expressed as secret note, informal voucher or the filaments of sun.Therefore, it requires high to technology controlling and process, so rate of finished products is lower usually, production cost is high.
3) pixel is difficult to further to dwindle: for the signal to noise ratio that maintains in the charge transfer constant, the CCD unit pixel dwindle requirement attenuate Oxide-Nitride (ON) thickness, and the reliability requirement of ON is constant, so further diminishing of CCD pixel has suitable difficulty.In addition, fringe field has also limited further dwindling of CCD pixel.
Above-described limitation is a problem in essence, is difficult to fundamentally solve.The influence of the technological factor of manufacturing CCD is very big.CCD is made on silicon integrated circuit, its technology basic composition comprises cleaning, oxidation, diffusion, photoetching, etching, ion injection, LPCVD, plasma growth and survey individual event technology, and the manufacturing of CCD is combined these individual event technologies exactly with different numbers and order.Oxidation, photoetching, ion inject.Oxidation is one of critical process during CCD makes, the SiO that oxidation generates
2Film has important effect in CCD, (1) is as protection and the passivating film of CCD.2) as the dielectric of grid oxygen among the CCD.3) as the separator between the polysilicon membrane, SiO
2Can prevent upper strata polysilicon and lower floor's inter polysilicon short circuit, oxide requires free of pinholes and space.In CCD makes, the mode of oxidizing of the dried oxygen-wet oxygen of more employing-dried oxygen combination.During CCD made, gate dielectric layer was by SiO
2One deck silicon nitride film of layer and upward regrowth thereof constitutes jointly, and this is because silicon nitride (Si
3N
4) dielectric constant approximately is the twice of silicon dioxide, but because the thermal coefficient of expansion of silicon nitride approximately is the twice of silicon, cause the contact between silicon nitride and the silicon bad, and SiO
2Approaching with the coefficient of expansion of Si, so form Si-SiO
2-Si
3N
4As gate dielectric layer.Domestic and international now when the dielectric layer of research metal-oxide-semiconductor, substitute SiO with the high-dielectric-coefficient grid medium layer
2Layer.The gate dielectric layer of research has: the metal oxide of III A family and III B family mainly comprises Al
2O
3, Y
2O
3, La
2O
3Deng; VI B family metal oxide mainly contains HfO
2, ZrO
2, TiO
2Deng; Stacking provisions such as HfO
2/ SiO
2, ZrO
2/ SiO
2Deng.
Different with CCD, each pixel of CMOS-APS all is separate, therefore the dislocation charge that does not need physical property in whole signals transmission, from having overcome the weakness of CCD in essence, but each pixel of CMOS-APS all comprises 1 photodiode and the transistor more than three.This framework can cause following problem:
I) dark current noise height: because CMOS-APS adopts diode as light-sensitive device, its dark current is than high similar two magnitudes of CCD.
Ii) effective quantum efficiency is difficult to improve: different with CCD, CMOS-APS also comprises at least three transistors except photodiode, and duty ratio is less than 60%.
Desirable image device should be: the array architecture of pixel+CMOS-APS of CCD, this also is a goal of the invention of the present invention.Existing floating-gate memory spare structure is to add one deck grid between the control gate of the MOS of routine structure and raceway groove, and this layer grid are surrounded by the oxide of densification, does not link to each other with extraneous, so be floating boom.On floating boom, be provided with control gate, with reference to Chinese patent CN1156337 etc.Floating-gate memory is a tunnel effect of utilizing electronics, and under certain electric field, electronics is injected in the floating boom in the compact oxide.The development of floating-gate memory comprises: adopt in the nanocrystalline embedding high K medium of Ge not only can to improve the reliability of device but also can reduce to write voltage and improve storage speed.Also be useful on the charge storage characteristic that contains Ge nanocrystalline M IS structure of nonvolatile memory.The MIS structure comprises the Al2O3 control gate by the method preparation of electron beam evaporation, the nanocrystalline and Al2O3 tunnel oxidation layer of Ge among the Al2O3.The C-V property list of this MIS structure under 1MHz reveals good electric property, and the flat band voltage drift is 0.96V, and charge storage density reaches 4.17 * 1012cm-2.Nanocrystalline the charge storage characteristic is along with the increase of frequency in the Al2O3 medium for Ge under the different frequency, and the drift of flat band voltage and charge stored number reduce (" functional material and device journal " 02 phase in 2007.
Three, summary of the invention
The present invention seeks to: propose a kind of new detector structure and method to set up, especially photosensitive compound medium grid MOSFET imaging detector (comprising infrared) to ultraviolet band.
The method to set up of photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector, the formation of each single-element detector is: the both sides above substrate P type semiconductor material are provided with the N type semiconductor district and constitute source electrode and drain electrode, being respectively equipped with two layers of dielectric material and controlling grid directly over the substrate, be provided with the photoelectron accumulation layer between two layers of dielectric material, described photoelectron accumulation layer is polysilicon, Si
3N
4, InGaN1, metal film or other electronic conductor or semiconductor; The control grid is polysilicon, metal or transparency conductive electrode;
Second dielectric that contacts with the control grid is the material that charge stored is lost to grid in the prevention photoelectron accumulation layer, and second dielectric is a broadband semiconductor; First insulating medium layer of substrate P type semiconductor material contact is effectively isolated raceway groove and photoelectron accumulation layer between source electrode and the drain electrode under grid low pressure, under the grid high pressure or photon energy when higher, electronics in the described raceway groove is swept the photoelectron accumulation layer; Source-drain electrode is hanging structure when collecting photoelectron and store photoelectron to photoelectron storage layer; First dielectric is the bottom medium, adopts silica, SiON or other high-k (high-k) medium; The material of second insulating medium layer is the top layer medium, adopts silicon oxide/silicon nitride/silicon oxide, silica/silica, silica, aluminium oxide or other high dielectric constant material;
The voltage difference of grid and substrate makes when wanting enough big that the photoelectron collected in the raceway groove can be by piercing into into the photoelectron accumulation layer then, and basalis or grid face have a place at least for to the transparent or semitransparent window of detector detection wavelength.The present invention is the structure of a similar floating-gate memory.
First dielectric is the bottom medium, and silica 1-10nm, high-k medium are (as HfO
2, Al
2O
3, ZrO
2, Y
2O
3, BaTiO
3, BaZrO
3, ZrSiO
4, Ta
2O
3Deng) 1-5nm (equivalent SiO
2Thickness), AlGaN1-100nm;
The material of second insulating medium layer is the top layer medium, silica/silica, silicon oxide/silicon nitride/silicon oxide, 12-20nm (equivalent SiO
2Thickness), silica 10-20nm, the about 10nm of aluminium oxide, silica 10-20nm, silica 10-100nm; Or the high-k medium, as HfO
2, ZrO
2, Y
2O
3, BaTiO
3, BaZrO
3, ZrSiO
4, Ta
2O
3Deng 1-5nm (equivalent SiO
2Thickness), AlGaN1-100nm.
The material of photoelectron accumulation layer and corresponding thickness: polysilicon 10-200nm, silicon nitride 3-10nm, InGaN10-200nm.
The both sides of substrate N type semiconductor material top are provided with P type semiconductor district formation source electrode and drain electrode does not exceed scope of the present invention yet.
1) described photoelectron accumulation layer photoelectron is collected and the collection and the storage of signal, read with reset mode and flow process as follows:
Photoelectronic collection and storage: add the positive bias pulse at grid, form depletion layer in the p N-type semiconductor N, when photon is absorbed, produce photoelectron in depletion layer, photoelectron is moved at the interface ordering about of grid voltage.Increase grid voltage, when voltage was enough big, photoelectron entered electric charge storage layer after by direct F-N tunnelling; If photon energy is big (greater than the Δ Ec of semiconductor and second layer dielectric) enough, photoelectron can direct Tunneling enter electric charge storage layer.Collecting the photoelectronic stage, source and leakage can be unsettled to prevent that electronics from injecting from source and leakage; The photoelectron accumulation layer can produce the drift of threshold voltage after depositing photoelectron in, by making photoelectron number in the photoelectron accumulation layer to the measurement of threshold voltage shift; As shown in Figure 5, common SiO
2Grid is replaced by the insulating barrier that double team polysilicon, and this layer constituted the grid of a suspension, i.e. composite dielectric gate by the polysilicon of double team (photoelectron accumulation layer).Being to be used to the grid controlled on the ordinary meaning on the composite dielectric gate, between control grid and outstanding complex media grid, be that SiO is arranged
2-Si
3N
4-SiO
2The dielectric isolation layer of forming.Bias voltage V when substrate and grid
Sb～+20V, the electronics in the raceway groove can enter in the composite dielectric gate by tunnelling, causes the increase of this MOSFET threshold voltage; Bias voltage V when substrate and grid
SbDuring～-10V, the tunneled holes in the raceway groove enters composite dielectric gate, with electron recombination in the composite dielectric gate, makes the threshold voltage of MOSFET return, and when superfluous hole is arranged in the grid, also can reduce the threshold value of MOSFET.Can determine threshold voltage by the electric current of measuring MOSFET, and then the quantity of electric charge in definite composite dielectric gate.
2) reading of signal: after photoelectron was collected the photoelectron accumulation layer, with source and substrate ground connection, miss+V (～1V), regulate the current potential+V of control grid, by direct measurement to electric current, or by leakage current with reference to the size of relatively coming to determine light signal of compound medium grid MOSFET electric current.The electric current and the photoelectronic relation of drain electrode are as follows:
Δ I wherein
DsBe the variation of drain current, N
FGBe the photoelectron number of storing in the photoelectron accumulation layer, C
TotAnd C
IPDBe respectively the electric capacity of total capacitance and the grid and the photoelectron accumulation layer of grid, W and L are respectively grid width and the length of this MOSFET, and μ is an electron mobility, V
DsBe the voltage difference of drain electrode with grid.In this process, the MOSFET that comprises the photoelectron accumulation layer is an amplifier, and it converts the photoelectron that photoelectron stores layer to current signal, and its function class is like the one-level amplifier of CCD and CMOS-APS;
3) reset: on grid, add back bias voltage Vg, substrate ground connection; When back bias voltage is enough high, the photoelectron that stores in the photoelectron accumulation layer is swept in the p N-type semiconductor N substrate by tunnelling.
Control method to threshold value: between control grid and composite dielectric gate is that SiO is arranged
2-Si
3N
4-SiO
2The dielectric isolation layer of forming; Bias voltage V when substrate and grid
Sb～+20V, the electricity in the raceway groove causes the increase of this MOSFET threshold voltage to enter in the composite dielectric gate by tunnelling; Bias voltage V when substrate and grid
SbDuring～-10V, the tunneled holes in the raceway groove enters composite dielectric gate, with electron recombination in the composite dielectric gate, makes the threshold voltage of MOSFET return, and when superfluous hole is arranged in the grid, reduces the threshold value of MOSFET; Can determine threshold voltage by the electric current of measuring MOSFET, and then the quantity of electric charge in definite composite dielectric gate.Photoelectron accumulation layer of the present invention is to utilize the operation principle of composite dielectric gate, with compound medium grid MOSFET become one have simultaneously that charge collection, photoelectron are measured and the addressing function, be used for photoelectron accumulation layer that imaging uses, constitute a pixel of a detector by one-transistor (switch type transistor), its array constitutes detector; Promptly constitute and be called photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector.
The invention has the beneficial effects as follows, the superiority of photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector is as follows: compare with CMOS-APS with CCD, photosensitive compound medium grid MOSFET has the advantage of a lot of CCD and CMOS-APS concurrently, but overcome their a lot of weakness, be that the ideal of image device of future generation is selected; Its characteristics and superiority comprise:
Scalability is fabulous: the yardstick of the compound medium grid MOSFET that contemporary flash memory technology uses is at 4～10F
2(F: minimum photoetching line dimension), when using the 50nm photoetching technique, the area of a photosensitive compound medium grid MOSFET may diminish to 0.01 micron
2, promptly at 1 micron
2On can make 100 photosensitive compound medium grid MOSFETs.In contrast to this, the pixel of CCD minimum is～3 microns of 3x
2, and CMOS-APS is～the 1x1 micron
2The use of photosensitive compound medium grid MOSFET technology can provide image devices such as CMOS-APS and CCD incomparable resolution, thereby make physical resolution be higher than optical resolution.
Compatible substantially with the flash memory production technology: the complex media gate technique of photosensitive compound medium grid MOSFET and standard is identical, can produce photosensitive compound medium grid MOSFET by standard compound medium grid MOSFET technology is finely tuned.
Leakage current is low: photosensitive compound medium grid MOSFET adopts the detection mechanism identical with CCD, so its leakage current is than low one to two magnitude of the CMOS-APS that adopts photodiode
Image taking speed is faster than CCD: although adopt the photoelectron identical with CCD to collect mechanism, photosensitive compound medium grid MOSFET is stored in the photoelectron of generation in the composite dielectric gate rather than in the raceway groove.Read output signal realizes by measuring threshold voltage (being the electric charge in the composite dielectric gate), thus do not need to carry photoelectron as CCD, so image taking speed can compare with CMOS-APS, and fast more a lot of than CCD.
Insensitive to defective workmanship: because photosensitive compound medium grid MOSFET does not need to carry photoelectron, the inefficacy of any one pixel can not influence other pixel, so it is responsive unlike CCD to defective workmanship, can be used to make the large area detector array.Can be prepared into the array of the various structures of similar existing NOR structure or enable nand gate.
Dynamic range is bigger than other structure: because photosensitive compound medium grid MOSFET signal readout can not influence signal itself fully, can support repeatedly to read.In practice, can regulate the size of output signal by the voltage that changes on the control gate, so can enlarge signal corresponding dynamic scope by reading with different gate voltages.This is the advantage that CCD and CMOS-APS do not have.
In addition, because photosensitive compound medium grid MOSFET technology and flash memory technology compatibility, this technology allows to make some memory cell on same chip, and some images that preset are deposited in the memory cell, is used for automatic Figure recognition.In the star-pursuing instrument, this function can add under the situation of Figure recognition function in nothing, helps related system to position automatically.In addition, we can also deposit the figure of needs coupling in the flash memory of making simultaneously with photosensitive compound medium grid MOSFET in, realize the terrain match function of on-chip.
Four, description of drawings
Fig. 1 is that panel detector structure energy band diagram of the present invention and photoelectron produce and transition graph
Fig. 2 is that panel detector structure energy band diagram of the present invention and photoelectron produce and move another schematic diagram
Fig. 3 is that panel detector structure signal of the present invention is read schematic diagram
Fig. 4 is the detector of the present invention schematic diagram that resets
Fig. 5 is the embodiment schematic diagram of second insulating medium layer of SiO2-Si3N4-SiO2 composition of the present invention
Fig. 6 is the present invention changes the output current of MOSFET by the quantity of electric charge in the change composite dielectric gate a schematic diagram
Fig. 7 is that the present invention is unsettled the source leakage, and compound medium grid MOSFET compares schematic diagram with the CCD structure roughly the same of band composite dielectric gate
Fig. 8 is that 3 compound medium grid MOSFETs on the word line of the present invention are in opening
Fig. 9 is 8x of the present invention 8 compound medium grid MOSFET array schematic diagrames
The collection of Figure 10 signal, read and the flow chart that resets
Five, embodiment
Photoelectron accumulation layer working mechanism and process are as follows:
1) collection of photoelectron collection and signal:
Energy band diagram and photoelectron produce and transition graph among Fig. 1,2: among the figure photoelectron produce 1, as hv＞semiconductor Eg (or Eg+ Δ Ec), photon is absorbed by semiconductor, can be from electronics of valence to conduction band;
2, photoelectron-transfer: when the voltage difference of grid and substrate is timing, photoelectron-transfer is to bottom medium and semi-conductive interface; When the voltage difference of grid and substrate is timing, if the Δ Ec of photon hv＞semiconductor Eg+ semiconductor and bottom medium, the photoelectron that excites can directly enter the photoelectron accumulation layer, moves to bottom medium and semi-conductive interface,
3, photoelectron is worn then: when the electric field in the bottom medium was enough strong, photoelectron pierced into then into the photoelectron accumulation layer;
4, photoelectron storage: when electric field was more weak in the top layer medium, photoelectron can be stored in the photoelectron accumulation layer.
Fig. 1,2 also is the compound medium grid MOSFET structure and collects photoelectronic fundamental diagram, motion and the CCD in photoelectron accumulation layer (as polysilicon) is identical for photoelectron, different is that CCD is stored in photoelectron in the raceway groove, is in the composite dielectric gate and composite dielectric gate is stored in the photoelectron accumulation layer to photoelectron.Photoelectron has three kinds of modes to enter the composite dielectric gate of photoelectron accumulation layer: i) photoelectron is introduced into raceway groove, enter composite dielectric gate by direct Tunneling again, ii) photoelectron enters composite dielectric gate by the F-N tunnelling, the compound medium grid MOSFET that is used for flash memory utilizes this mechanism that electric charge is deposited in composite dielectric gate, iii) the photoelectron direct Tunneling enters composite dielectric gate, the similar PMT photoelectron emissions of this process, difference be PMT photoelectron emissions in vacuum, and this process is advanced photoelectron emissions in the composite dielectric gate.It should be noted that and collecting the photoelectronic stage that source and leakage must be unsettled to prevent that electronics from injecting from source and leakage.Photoelectronic in addition collection process and can separate (perhaps not separated) to the process that photoelectron injects composite dielectric gate can use lower voltage to reduce dark current in the photoelectron stage of collecting like this.Composite dielectric gate is that electric charge storage layer also can adopt metal membrane material.
2) reading of signal:
After photoelectron was collected photoelectron accumulation layer composite dielectric gate, source ground connection, miss+V (～1V), regulate the current potential+V of control grid, by direct measurement to electric current, or by leakage current with reference to the size of relatively coming to determine light signal of compound medium grid MOSFET electric current.
In this process, the MOSFET of photoelectron accumulation layer composite dielectric gate and formation is an amplifier, and current signal is converted to voltage signal, and its function class is like the one-level amplifier of CCD and CMOS-APS.Different is, the photoelectron of CCD and CMOS-APS can change the current potential on its amplifier control grid, is threshold voltage and the photoelectron in the compound medium grid MOSFET of the present invention changes.In addition, in the signal readout, be stored in that photoelectron can not be affected fully in the composite dielectric gate, can allow to read repeatedly.
Referring to Fig. 3: Δ I
DsVariation (Δ I for drain current
Ds: have or not photoelectronic leakage current to change in the photoelectron accumulation layer), N
FGBe the photoelectron number of storing in the photoelectron accumulation layer, C
TotAnd C
IPDBe respectively (with the basalis) total capacitance (parasitic capacitance that comprises source and leakage) of grid and the electric capacity of grid and photoelectron accumulation layer, W and L are respectively grid width and the length of this MOSFET, and μ is an electron mobility, V
DsBe the voltage difference of drain electrode with grid.In this process, the MOSFET that comprises the photoelectron accumulation layer is an amplifier, and it converts the photoelectron that photoelectron stores layer to current signal, and its function class is like the one-level amplifier of CCD and CMOS-APS;
3) reset at control and add back bias voltage Vg, substrate ground connection on the grid; Increasing back bias voltage Vg scans out the photoelectron in the photoelectron accumulation layer composite dielectric gate photoelectron accumulation layer composite dielectric gate or the hole is swept photoelectron accumulation layer composite dielectric gate by wearing then; Use this method can reach the purpose that resets; In concrete the application, consider the problem of " over-erasure ", also can be combined in grid and add positive bias, Vt (equal the signal collection current potential of grid and wipe the poor of reset potential) is adjusted to a specific value.And referring to Figure 10.
4) the present invention can be prepared into photoreactivation medium grid MOSFET array according to existing flash technology.
The complex media gate technique of extensive use in flash memory has become a kind of very mature technique.Comprise 10 in the 1Gb flash memory
9Individual compound medium grid MOSFET, in the past ten years, people develop various compound medium grid MOSFET assembling structure all can be used for the present invention.In the complex media gate technique, Fig. 8 and Fig. 9 have provided two kinds of available array architectures.
Fig. 4 detector resets in the schematic diagram, adds back bias voltage on grid, and substrate ground connection increases Vg the photoelectron in the photoelectron accumulation layer is scanned out the photoelectron accumulation layer or the hole is swept the photoelectron accumulation layer by wearing then.Use this method can reach the purpose that resets.In concrete the application, consider the problem of " over-erasure ", can be combined in grid and add positive bias, Vt is adjusted to a specific value.
SiO among Fig. 5
2-Si
3N
4-SiO
2The embodiment of second insulating medium layer of forming: process 1 and 3: λ＞387nm photoelectron → raceway groove → composite dielectric gate; Process 2: λ＜387nm photoelectron → composite dielectric gate.Φ s refers to when grid voltage during for+20V among Fig. 5, pressure drop in semiconductor.
The embodiment of size range of material that constitutes detector of the present invention is as (but being not limited to) table 1:
Grid top layer medium photoelectron storage medium bottom dielectric semiconductor layer
1 material polysilicon oxidation silicon/nitrogenize silicon/oxidative silicon polysilicon oxidation silicon silicon
Thickness--12-20nm (equivalent SiO2 thickness) 10-200nm 1-10nm---
2 material polysilicon oxidation silicon silicon nitride silicon oxide silicons
Thickness--10-20nm 3-10nm 1-10nm---
3 material of tungsten aluminium oxide silicon nitride silicon oxide silicons
Thickness--Yue 10nm 3-10nm 1-10nm---
4 material polysilicon oxidation policrystalline silicon silicon high-k medium (Hf0) silicon
Thickness--10-20nm 10-200nm 1-5nm (equivalent SiO2)---
5 material metal silica InGaN AlGaN AlGaN
Thickness--10-100nm 10-200nm 1-100nm---
6 material metal silicon oxide/silicon nitride/silicon oxide polysilicon oxidation silicon-carbon-silicon carbides
Thickness--12-20nm (equivalent SiO2 thickness) 10-200nm 1-10nm---
According to the example structure of table 1, concrete detector embodiment such as table 2:
Grid top layer medium photoelectron storage medium bottom dielectric semiconductor layer
Material polysilicon oxidation silicon/alumina/silica polysilicon oxidation silicon silicon
The decision of 1 thickness technology decision 5nm/5nm/5nm 100nm 5nm technology
2 all the same 5nm/6nm/5nm 100nm 5nm are all the same
3??????????????????5nm/7nm/5nm?????????????100nm????????????5nm
4??????????????????5nm/8nm/5nm?????????????100nm????????????5nm
5??????????????????5nm/9nm/5nm?????????????100nm????????????5nm
6??????????????????5nm/10nm/5nm????????????100nm????????????5nm
6nm/7nm/6nm?????????????100nm????????????5nm
7??????????????????7nm/7nm/7nm?????????????100nm????????????5nm
8??????????????????8nm/7nm/8nm?????????????100nm????????????5nm
9??????????????????9nm/7nm/9nm?????????????100nm????????????5nm
10?????????????????10nm/7nm/7nm????????????100nm????????????5nm
11?????????????????5nm/10nm/5nm????????????100nm????????????4nm
12?????????????????5nm/10nm/5nm????????????100nm????????????3nm
13?????????????????5nm/10nm/5nm????????????100nm????????????2nm
The concrete detector embodiment of table 2-3 all is the detectors that can reach effect of the present invention.The structure of other detector in the table 1 also can be analogous to the detector of table 2-3 structure, owing to adopt identical or compatible semiconductor technology, the structure of other detector of table 1 of the present invention also is fully feasible on prepared, in working mechanism fully with working frame of the present invention, on effect can be analogous to the table 2-3 example structure.
Concrete detector embodiment, table 3
Grid top layer medium photoelectron storage medium bottom dielectric semiconductor layer
Material polysilicon oxidation silicon/nitrogenize silicon/oxidative silicon polysilicon oxidation silicon silicon
The decision of 1 thickness technology decision 10nm/7nm/7nm 80nm 9nm technology
2 all the same 10nm/7nm/7nm 100nm 9nm are all the same
3?????????????????????10nm/7nm/7nm???????????150nm????????????9nm
4?????????????????????10hm/7nm/7nm???????????200nm????????????9nm
5?????????????????????10nm/7nm/7nm???????????300nm????????????9nm
6?????????????????????10nm/7nm/7nm???????????400nm????????????9nm
7?????????????????????10hm/7nm/7nm???????????500nm????????????9nm
8?????????????????????10hm/7nm/7nm???????????600nm????????????8nm
9?????????????????????10nm/7nm/7nm???????????600nm????????????7nm
10????????????????????10nm/7nm/7nm???????????600nm????????????6nm
11????????????????????10nm/7nm/7nm???????????600nm????????????5nm
12????????????????????10nm/7nm/7nm???????????600nm????????????4nm
13????????????????????10nm/7nm/7nm???????????600nm????????????3nm
14????????????????????10nm/7nm/7nm???????????600nm????????????2nm
15????????????????????7nm/6nm/5nm????????????80nm?????????????9nm
16????????????????????7nm/6nm/5nm????????????100nm????????????9nm
17????????????????????7nm/6nm/5nm????????????150nm????????????9nm
18????????????????????7nm/6nm/5nm????????????200nm????????????9nm
19????????????????????7nm/6nm/5nm????????????300nm????????????9nm
20????????????????????7nm/6nm/5nm????????????400nm????????????9nm
21????????????????????7nm/6nm/5nm????????????500nm????????????9nm
22????????????????????7nm/6nm/5nm????????????600nm????????????8nm
23????????????????????7nm/6nm/5nm????????????60nm?????????????7nm
24????????????????????7nm/6nm/5nm????????????600nm????????????6nm
25????????????????????7nm/6nm/5nm????????????600nm????????????5nm
26????????????????????7nm/6nm/5nm????????????600nm????????????4nm
27????????????????????7nm/6nm/5nm????????????600nm????????????3nm
28????????????????????7nm/6nm/5nm????????????600nm????????????2nm
29????????????????????7nm/7nm/7nm????????????600nm????????????5nm
Fig. 6 can change the schematic diagram of the output current of MOSFET, Vgate=Vg among Fig. 6 by changing the quantity of electric charge in the composite dielectric gate; The foregoing description is increased grid voltage, when with the voltage difference of substrate enough big the time, for polysilicon/ONO/ polysilicon/SiO
2Structure, this value for＞+18V, embodiment gets grid voltage and reaches 20V, for polysilicon/ONO/Si
3N
4/ SiO
2Structure, this value is+12V; Relevant with the material behavior of detector, enter electric charge storage layer after making the direct F-N tunnelling of photoelectron.
Among Fig. 6 a: when the voltage difference of grid and substrate is timing, photoelectron-transfer is to bottom medium and semi-conductive interface; When the voltage difference of grid and substrate is timing, if the Δ Ec of photon hv＞semiconductor Eg+ semiconductor and bottom medium, the photoelectron that excites can directly enter the photoelectron accumulation layer, moves to bottom medium and semi-conductive interface,
Fig. 6 b represents that photoelectron wears then: when the electric field in the bottom medium was enough strong, photoelectron pierced into then into the photoelectron accumulation layer;
Photoelectron storage: when electric field in the top layer medium a little less than, when the electric current that photoelectron is tunneling to grid from accumulation layer can be ignored, photoelectron can be stored in the photoelectron accumulation layer.
Fig. 6 c is the structure of composite grid trnasistor detector, wherein Δ V
TFor enter the variations in threshold voltage that accumulation layer causes, I owing to photoelectron
DrainBe drain current, Q
FGBe the photoelectron total charge dosage of storing in the accumulation layer, C
IPDBe the electric capacity of grid and accumulation layer, V
GateBe the voltage that is added on the grid.Total amount of electric charge in the skew of threshold voltage and the photoelectron accumulation layer is directly proportional.
Fig. 6 d has provided drain current, I
DrainWith grid voltage V
GateGraph of a relation.After wherein left side curve resetted, the right curve was to inject photoelectron in the photoelectron accumulation layer.
When resetting: on grid, add back bias voltage Vg, substrate ground connection; Scope when the sufficiently high value of back bias voltage: for polysilicon/ONO/ polysilicon/SiO
2Structure, this value for＞-18V. for polysilicon/ONO/Si
3N
4/ SiO
2Structure, this value is-12V.
ITO on basalis or the grid face, metal film or semi-conducting material film all constitute easily surveys the transparent or semitransparent window of wavelength to detector.
Use lower voltage to reduce dark current in the photoelectron collection stage: to polysilicon/ONO/ polysilicon/SiO
2Structure, this value for＞+10-15V; . for polysilicon/ONO/Si
3N
4/ SiO
2Structure, this value is+5V-10V.
Fig. 7 is unsettled the source leakage, the structural representation of the CCD of compound medium grid MOSFET → band composite dielectric gate;
3 compound medium grid MOSFETs on Fig. 8 word line 3 are in opening;
Fig. 9 is a 8x 8 compound medium grid MOSFET arrays.Red (light color) horizontal line is public control gate among the figure, and the black vertical line is public source and leakage, and what iris out with blueness (dark color) is the compound medium grid MOSFET of being read.What show is a kind of combo architectures of 8x 8 compound medium grid MOSFETs, what laterally red line (light color) showed is the control gate that 8 compound medium grid MOSFETs are shared, the black vertical line is source and the leakage of sharing, and each pixel only comprises one by photosensitive compound medium grid MOSFET.When at a certain public control-grid voltage in greater than threshold voltage the time, can be by the selection source and leak the quantity of electric charge on the composite dielectric gate read on the MOSFET different on this control line.In Fig. 9, first, fourth, seven MOSFET under the 4th public control gate are being in the state of reading.Process of the present invention and the identical or complete compatibility of existing Si semiconductor technology (flash memory preparation technology).Figure 10 be signal collection, read and the flow chart that resets.
Idi among Figure 10: initial drain current; Dref: drain electrode reference current; ε: the deviation of endurable maximum drain current and reference current.
The low drain circuit of the existing CCD of the present invention, high duty ratio characteristics have the advantage of CMOS-APS framework again, are planted in the flash memory technology of contemporary high mature simultaneously, directly use flash technology, design, manufacturing platform; Make pixel reach minimum (the flash cell size can to～80nmx80nm), picture element density can reach 100/ μ m
2(far surpass optical resolution ,～1 micron; Integrated jumbo unit makes the potential breakthrough of absolute picture number 1G; Well depth (well capacity)＞5000e-/μ m
2, can improve the image quality of small pixel; Can be embodied as picture, the electronic map match function is integrated in same chip; Response range: 400nm-1000nm or broadband more, well depth:＞5000e-/μ m
2Dynamic range: greater than 70dB; Dark current: 10nA/cm
2Power consumption: 100mW.
Claims (12)
1. the method to set up of photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector, the formation that it is characterized in that each single-element detector is: the both sides above substrate P type semiconductor material are provided with the N type semiconductor district and constitute source electrode and drain electrode, being respectively equipped with two layers of dielectric material and controlling grid directly over the substrate, be provided with the photoelectron accumulation layer between two layers of dielectric material, described photoelectron accumulation layer is polysilicon, Si
3N
4, InGaN1, metal film or other electronic conductor or semiconductor; The control grid is polysilicon, metal or transparency conductive electrode;
Second dielectric that contacts with the control grid is the material that charge stored is lost to grid in the prevention photoelectron accumulation layer, and second dielectric is a broadband semiconductor; First insulating medium layer of substrate P type semiconductor material contact is effectively isolated raceway groove and photoelectron accumulation layer between source electrode and the drain electrode under grid low pressure, under the grid high pressure or photon energy when higher, electronics in the described raceway groove is swept the photoelectron accumulation layer; Source-drain electrode is hanging structure when collecting photoelectron and store photoelectron to photoelectron storage layer; First dielectric is the bottom medium, adopts silica, SiON or other high dielectric constant; The material of second insulating medium layer is the top layer medium, adopts silicon oxide/silicon nitride/silicon oxide, silica/silica, silica, aluminium oxide or other high dielectric constant material;
The voltage difference of grid and substrate makes when wanting enough big that the photoelectron collected in the raceway groove can be by piercing into into the photoelectron accumulation layer then, and basalis or grid face have a place at least for to the transparent or semitransparent window of detector detection wavelength.
2. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 is characterized in that first dielectric for the bottom medium is: silica 1-10nm, HfO
2, Al
2O
3, ZrO
2, Y
2O
3, BaTiO
3, BaZrO
3, ZrSiO
4Or Ta
2O
3, its equivalent SiO
2Thickness is 1-5nm, or AlGaN1-100nm;
Second insulating medium layer is the top layer medium: silicon oxide/silicon nitride/silicon oxide, equivalent SiO
2Thickness is 12-20nm, silica 10-20nm, aluminium oxide 10nm, silica 10-20nm, silica 10-100nm, HfO
2, ZrO
2, Y
2O
3, BaTiO
3, BaZrO
3, ZrSiO
4, or Ta
2O
3, its equivalent SiO
2Thickness is 1-5nm, or AlGaN1-100nm.
Photoelectron accumulation layer: polysilicon 10-200nm, silicon nitride 3-10nm or InGaN 10-200nm.
3. the method to set up of photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector according to claim 1 and 2, it is characterized in that described photoelectron accumulation layer is collected photoelectron and the collection and the storage of signal, read with reset mode and flow process as follows:
Photoelectronic collection and storage: add the positive bias pulse at grid, form depletion layer in substrate p N-type semiconductor N, when photon is absorbed, produce photoelectron in depletion layer, photoelectron is moved at the interface ordering about of grid voltage; Increase grid voltage, when voltage was enough big, photoelectron entered electric charge storage layer by direct back F-N tunnelling; If photon energy is enough big, greater than the Δ Ec of semiconductor and second layer dielectric, but the photoelectron direct Tunneling enters electric charge storage layer;
Collecting the photoelectronic stage, source and leakage can be unsettled to prevent that electronics from injecting from source and leakage; The photoelectron accumulation layer can produce the drift of threshold voltage after depositing photoelectron in, by the measurement of threshold voltage shift being made photoelectron number in the photoelectron accumulation layer; Bias voltage V when substrate and grid
Sb～+20V, the electronics in the raceway groove enters in the composite dielectric gate of electronics accumulation layer formation by tunnelling, causes the increase of this MOSFET threshold voltage; Bias voltage V when substrate and grid
SbDuring～-10V, the tunneled holes in the raceway groove enters composite dielectric gate, with electron recombination in the composite dielectric gate, makes the threshold voltage of MOSFET return, and when superfluous hole is arranged in the grid, also can reduce the threshold value of MOSFET; Determine threshold voltage by the electric current of measuring MOSFET, and then the quantity of electric charge in definite composite dielectric gate;
2) reading of signal: after photoelectron was collected the photoelectron accumulation layer, with source and substrate ground connection, miss+V (～1V), regulate the current potential+V of control grid, by direct measurement to electric current, or by leakage current with reference to the size of relatively coming to determine light signal of compound medium grid MOSFET electric current, the electric current of drain electrode and photoelectronic relation are as follows:
Δ I wherein
DsBe the variation of drain current, N
FGBe the photoelectron number of storing in the photoelectron accumulation layer, C
TotAnd C
IPDBe respectively the electric capacity of total capacitance and the grid and the photoelectron accumulation layer of grid, W and L are respectively grid width and the length of this MOSFET, and μ is an electron mobility, V
DsBe the voltage difference of drain electrode with grid;
3) reset: on grid, add back bias voltage Vg, substrate ground connection; When back bias voltage is enough high, the photoelectron that stores in the photoelectron accumulation layer is swept in the p N-type semiconductor N substrate by tunnelling.
4. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 3, the process that it is characterized in that injecting composite dielectric gate with photoelectronic collection with photoelectron separately uses lower voltage to reduce dark current in the photoelectron collection stage like this.
5. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2 is characterized in that single-element detector is prepared into array and constitutes the photoreactivation dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector.
6. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 3 is characterized in that the control method to threshold value: between control grid and composite dielectric gate is that SiO is arranged
2-Si
3N
4-SiO
2The dielectric isolation layer of forming; Bias voltage V when substrate and grid
Sb～+20V, the electricity in the raceway groove causes the increase of this MOSFET threshold voltage to enter in the composite dielectric gate by tunnelling; Bias voltage V when substrate and grid
SbDuring～-10V, the tunneled holes in the raceway groove enters composite dielectric gate, with electron recombination in the composite dielectric gate, makes the threshold voltage of MOSFET return, and when superfluous hole is arranged in the grid, reduces the threshold value of MOSFET; Can determine threshold voltage by the electric current of measuring MOSFET, and then the quantity of electric charge in definite composite dielectric gate.
7. according to claim 2 or 3 described photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector methods to set up, it is characterized in that first dielectric is that the bottom medium is silica 1-10nm; The material of second insulating medium layer is that the top layer medium is silicon oxide/silicon nitride/silicon oxide or silica/silica, equivalent SiO2 thickness 12-20nm, and photoelectron storage medium polysilicon 10-200nm, grid is a polysilicon.
8. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2 is characterized in that first dielectric is that the bottom medium is silica 1-10nm; The material of second insulating medium layer is top layer medium silica 10-20nm, and the photoelectron storage medium is silicon nitride 10-20nm, and grid is a polysilicon.
9. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2 is characterized in that grid is a tungsten, top layer medium aluminium oxide 10nm, photoelectron storage medium silicon nitride 3-10nm, bottom medium silica 1-10nm.
10. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2, it is characterized in that grid is a polysilicon, top layer medium silica 10-20nm, photoelectron storage medium polysilicon 0-200nm, bottom medium high dielectric constant, equivalent SiO
2Thickness 1-5nm.
11. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2, it is characterized in that grid is a metal, top layer medium silica 10-100nm, photoelectron storage medium InGaN10-200nm, bottom medium A lGaN1-100nm, base material AlGaN.
12. photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector method to set up according to claim 1 and 2 is characterized in that grid is a metal, second insulating medium layer is that the top layer medium is silicon oxide/silicon nitride/silicon oxide or silica/silica, equivalent SiO
2Thickness 12-20nm, photoelectron storage medium polysilicon 10-200nm, the bottom medium is silica 1-10nm, base material is a carborundum.
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| US13/126,079 US8604409B2 (en) | 2009-02-18 | 2010-02-10 | Photosensitive detector with composite dielectric gate MOSFET structure and its signal readout method |
| KR1020117021893A KR101563770B1 (en) | 2009-02-18 | 2010-02-10 | Photosensitive detector with composite dielectric gate mosfet and singal reading method thereof |
| EP10743414.4A EP2400547B1 (en) | 2009-02-18 | 2010-02-10 | Photosensitive detector with composite dielectric gate mosfet and singal reading method thereof |
| JP2011549425A JP5939703B2 (en) | 2009-02-18 | 2010-02-10 | Photosensitive detector having composite dielectric gate MOSFET structure and signal reading method thereof |
| PCT/CN2010/070612 WO2010094233A1 (en) | 2009-02-18 | 2010-02-10 | Photosensitive detector with composite dielectric gate mosfet and singal reading method thereof |
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