JPH0782760B2 - Image memory device - Google Patents

Description

The present invention relates to an image memory device having a photoelectric conversion function and a memory function.

[Conventional technology]

Figure 2 is from Electronics Magazine, July 1982 (p.681-7
13} is a block diagram showing an image processor having a conventional three-dimensional circuit element structure described in Sakamoto's paper "Advanced electronics technology of Japan in the next-generation industrial substrate technology research and development system" of 13}. As shown in the figure, a photoelectric conversion unit 1 such as a CCD type image pickup device including a scanning circuit for scanning each pixel is formed in the uppermost layer, and the photoelectric conversion unit 1 as the processing circuit is formed below the photoelectric conversion unit 1. A D conversion unit 2, a memory 3 composed of a semiconductor memory such as SRAM in a lower layer thereof, a calculation unit 4 for performing image processing in a lower layer thereof, and a power supply / driving unit 5 in a lower layer thereof. These disturbing circuits 1 to 5 are formed in individual single crystal layers 6 and are separated from each other by providing an insulating film 7 between the single crystal layers 6, 6.

In such a configuration, as shown in the block diagram of FIG. 3, the optical signal charges photoelectrically converted by the image sensor 1a of the photoelectric conversion unit 1 are transferred to the A / D conversion circuit 2 via the scanning circuit 1b. The digital signal is A / D converted by the A / D conversion circuit 2 and stored in the memory 3 as a digital signal. Further, at the time of reading, the arithmetic unit 4 extracts the stored contents from the memory 3 and outputs a video signal.

FIG. 4A is a cross-sectional view showing one pixel of a solid-state imaging device having an SOI structure as an example of the photoelectric conversion circuit 1 shown in FIG. 2, and FIG. It is a figure shown about a minute. The photoelectric conversion circuit shown here is VL
S. Hirose et al.'S paper "10-bit Nilia Image Sensor Created in Two-Layer Active Region" in SI Technology Symposium [May, 1985].

As shown in FIG. 3A, a SiO ₂ film 11 is formed on a semiconductor substrate 10, and a p-type silicon region 12 is formed on the SiO ₂ film 11 (SOI structure). The n-type silicon regions 13 and 14 are formed in the upper layer portion of the p-type silicon region 12, and the SiO ₂ film 15 is formed on the p-type silicon region 12 between the n-type silicon regions 13 and 14.
A polysilicon gate 16 is formed through. Further, an Al wiring 17 is formed on the n-type silicon region 13 and an Al wiring 18 is formed at an end portion on the p-type silicon region 12 so as to penetrate the SiO ₂ film 15. The SiO ₂ film 15 is a polysilicon gate 1
6 and the p-type silicon region 12 are covered. 20 is the incident light.

P-type silicon region 12 and n-type silicon region of FIG. 4 (a)
The pn junction with 14 forms the photodiode PD shown in FIG. 4 (b), and the p-type silicon region 12, the n-type silicon regions 13 and 14 and the polysilicon gate 16 form the photodiode PD in FIG. 4 (b). The transistor T shown is formed. Also,
The polysilicon gate 16 functions as a horizontal signal line, and the Al wiring layer 17 functions as a vertical signal line.

In such a configuration, when the light 20 is applied to the photodiode PD, charges are generated in the photodiode PD, and a predetermined voltage is applied to the polysilicon gate 16 to turn on the Al wiring via the transistor T that is turned on. Layer 17
The photoelectric conversion and the signal scanning are performed by the current flowing in the.

FIG. 5 is a circuit configuration diagram showing a basic configuration of a conventional solid-state image pickup device which is a photoelectric conversion circuit having a laminated structure. As shown in the figure, the photodiode PD array is provided in the uppermost layer L1, and the scanning circuit is provided in the layer L2 below the uppermost layer L1 by the scanning switching transistors ST and the like. Incidentally, 1 is a scanning signal line.

However, in the photoelectric conversion circuit shown in FIGS. 4 and 5, the Al wiring layer 17, the scanning signal line l1 and the like are provided in the uppermost layer in addition to the photodiode PD that performs photoelectric conversion, and therefore the opening is accordingly formed. The problem is that the rate is lowered and the photoelectric conversion sensitivity is impaired.

On the other hand, there is a fixed image sensor in which the photoelectric conversion function is provided in all the uppermost layers, a scanning unit is provided in the lower layer, and the photoelectric conversion sensitivity is improved by increasing the aperture ratio to 100%. FIG. 6 is a sectional view showing an example thereof. This figure shows a fixed image pickup device having one pixel. This solid-state image pickup device is described in the paper "Design, Prototype, and Characteristic Evaluation of Single-Plate Color Solid-State Image Pickup Device Using Amorphous Si" by Mr. Maji et al. In Technical Report of Television Society (Vol. It is disclosed.

As shown in FIG. 6, as a photoelectric conversion surface, an image sensor portion 1a having an amorphous Si: H film 31 formed on the entire upper layer portion.
And a traveling circuit section 1b formed thereunder.

In the image sensor unit 1a, a glass plate 32, a color filter 33, an adhesive 34, a transparent electrode 35, and an amorphous Si; H film 31 are formed from the uppermost layer. On the other hand, the scanning circuit 1b includes n ⁺ source and drain diffusion layers 22 and 23 formed in the upper layer portion of the p layer 21, and these n
⁺ A polysilicon gate 25 formed by covering an insulating film 24 around the p region 21 between the source / drain diffusion layers 22 and 23.
Form a switching transistor for the scanning circuit. Further, the polysilicon gate 25 functions as a horizontal signal line.

The n ⁺ source diffusion layer 22 is electrically connected to the amorphous Si; H film 31 for photoelectric conversion through the first Al layer 26 and the second Al layer 27. On the other hand, an Al vertical signal line 28 is formed on the n ⁺ drain diffusion layer 23. In addition, 29 is an interlayer insulating film, 30 is n
Type Si substrate.

By thus providing the entire upper layer with a photoelectric conversion function, the aperture ratio is set to 100% and the photoelectric conversion sensitivity is improved. However, even when the photoelectric conversion sensitivity is increased in this way, the analog electric signal photoelectrically converted as shown in FIGS. 2 and 3 is stored in the memory 3 after being digitized by the A / D conversion circuit 2. There is a need to. Therefore, there is a problem that a time-series signal conversion means is required, and the configuration is complicated by the addition of the A / D converter.

As an image memory device for avoiding the above problems,
In IEEE Electron Device Magazine ED-32 (1985)
H. Yamasaki et al.'S paper, "Solid-state image sensor with built-in MNOS memory gate," has been disclosed.

7 (a) and 7 (b) are a circuit diagram showing the basic structure of the image memory device and a sectional view showing the sectional structure of one pixel.

In FIG. 7A, 41 is a horizontal scanning circuit, 42 is a vertical scanning circuit, 43 is a read / write switching circuit, 44 is a horizontal switch MOS transistor, 45 is an integration circuit for detecting a read signal, and VS is a video signal output. Signal line, V _OUT is video output, PCD is overflow drain terminal, P _OG is overflow gate terminal, l2 is Al horizontal selection, l3 is Al vertical signal line, and l4 is overflow drain line. Reference numeral 46 denotes an image memory constituent portion for one pixel, which is composed of a photodiode PD, transistors T1 to T3 each having an overflow gate, a MNOS memory gate and a transfer gate.

As shown in FIG. 7B, each pixel 46 has four n ⁺ diffusion layers 51 to 54 formed on the upper layer of the p-type Si substrate 50. n ⁺ diffusion layer 5
An overflow gate OG made of polysilicon is formed on the p-type Si substrate 50 between 1, 52 via a SiO ₂ film 55.
Further, the MNOS memory gate MG made of polysilicon is formed on the p-type Si substrate 50 between the n ⁺ diffusion layers 52 and 53 by the SiO ₂ film 55 and the Si ₃ N ₄ film 5.
A transfer gate TG made of polysilicon is formed on the p-type Si substrate 50 between the n ⁺ diffusion layers 53 and 54 via the SiO ₂ film 55. Then, the n ⁺ diffusion layers 51 and 52 and the overflow preparative gate OG by the transistor T1, variance n ⁺ diffusion layer
52,53 and MNOS memory gate MG for memory transistor T2
By the n ⁺ diffusion layers 53 and 54 and the transfer gate TG.
3, a photodiode PD is formed by a ph junction between the n ⁺ diffusion layer 52 and the p-type Si substrate 50. Transistor mentioned above
T2 and T3 form a dual gate transistor. Further, the Al vertical signal l3 is formed on the n ⁺ diffusion layer 54 through the SiO ₂ film 55 and the Si ₃ N ₄ film 56, and the SiO ₂ film 55, S is formed on the n ⁺ diffusion layer 51.
An overflow drain line l4 is formed so as to penetrate the i ₃ N ₄ film 56.

MNOS memory gate MG in the memory transistor T2 is Si
By the composite film composed of the O ₂ film 55 and the Si ₃ N ₄ film 56,
When you want to write a signal, you are storing it. That is, a part of the photoexcited charge is partially absorbed in the Si ₃ N ₄ film 56 and the SiO ₂ film
Image information is stored in analog by trapping in traps at the interface between 5 and Si ₃ N ₄ film 56 and changing the flat band voltage V _FB . Also, a transistor T3 having a transfer gate TG
Turns off to prevent the electric charge accumulated in the memory transistor T2 from flowing out to the Al vertical signal line l3. The overflow gate OG, n ⁺ diffusion layer 51 of the transistor T1 is connected to the overflow gate terminal P _OG and the overflow drain terminal P _OD , respectively, so that the preset operation of the photodiode PD is performed at the time of writing as described later. Further, at the time of image capturing, when the photodiode PD is irradiated with strong light, it also serves as an overflow drain that sweeps out charges overflowing from the photodiode PD and suppresses blooming. Further, the overflow gate terminal P _OG and the overflow drain terminal P _OD serve as a generation source of a certain amount of electric charge during reading, as will be described later.

The read / write switching circuit 43 supplies a positive write voltage or a negative erase pulse voltage to the MN of the memory transistor T2.
Memory transistor T2 by giving to OS memory gate MG
Can be written to and erased. On the other hand, in reading the stored contents of the pixel 46 (including during imaging), the horizontal scanning circuit 41 and the vertical scanning circuit 42 apply a scanning pulse via the Al vertical signal line l3 and the Al horizontal selection line l2, respectively. This can be done by driving and reading the information.

FIG. 8 is a potential distribution diagram for explaining the write operation to the image memory shown in FIG. 7, and in particular, the n ⁺ diffusion layer 52 forming the photodiode PD and the MNOS memory gate.
The potential distribution on the surface of the p-type silicon substrate 1 under the MG (hereinafter referred to as “substrate surface”) is shown. In the figure, the lower side is the positive potential direction. Hereinafter, the writing principle will be described with reference to the figure. .

First, from the overflow gate terminal P _OG , the transistor T
Apply a reset pulse to the overflow gate OG of 1.
As shown in FIG. 3A, the photodiodes of all pixels 46
The electric potential of the n ⁺ diffusion layer 52 forming the PD is set to the preset electric potential V _SO, and the electric charge amount E0 in the preset state is determined.

In this state, the light is fed to the photodiode for a certain integration period Ti.
Upon incidence on the PD, the photo-excited optical signal charges are accumulated in the n ⁺ diffusion layer 52 and fall to the potential or V _S as shown in FIG. Note that E2 represents the amount of optical signal charge. This behavior is IEEE
J. Solid-State Circuits, Vol SC-2, no.12 p.65-73 S
GP Weckke's paper “Operation of p.
−n junction photodetectors in a phonton flux inte
This is equivalent to the PFI (Photon-Flus Integration) mode in a normal MOS type solid-state imaging device disclosed in "gration mode".

After that, when a positive write pulse voltage is applied to the MNOS memory gate MG of the memory transistor T2, the MNOS memory gate MG
The substrate surface potential φ MG under _MG rises, and the charges accumulated in the n ⁺ diffusion layer 52 are transferred to the MNOS memory gate as shown in FIG.
Transferred in BBD mode under MG. And n ⁺ diffusion layer 52 and M
The charges accumulated under the NOS memory gate MG reach an equilibrium state at a balanced equilibrium potential V _SF , and the charge transfer is completed as shown in FIG. E1 is the preset charge amount E0
Is a transferred bias charge amount.

After that, as shown in FIG. 7E, a part of the charges on the substrate surface under the MNOS memory gate MG is tunnel-injected into the thin SiO ₂ film 55 to form a trap at the interface between the SiO ₂ film 55 and the Si ₃ N ₄ film 56. To be captured.
As a result, the flat band voltage V _FB of the MNOS memory gate MG in the memory transistor T2 rises. The flat band voltage V _FB has negative correlation with the substrate surface potential phi _MG under MNOS memory gate MG, if the same voltage applied to the MNOS memory gate MG, the substrate surface potential higher flat band voltage V _FB φ _MG becomes low. In this way, the optical information photoelectrically converted by the photodiode PD is stored as analog information in the MNOS memory gate MG of the memory transistor T2 as a displacement of the flat band voltage V ₁₈ . Therefore, it is not necessary to separately provide the A / D conversion unit.

At this time, as the preset voltage V _SO is lower, the preset charge EO is larger even with the same optical signal charge amount E2. Therefore, the potential of the n ⁺ diffusion layer 52 after the signal charge is accumulated and the positive write pallet is applied.
The difference between the substrate surface potential phi _MG under MNOS memory gate MG is increased. As a result, the equilibrium potential V _SF rises as the bias charge amount E1 increases, and the charge amount stored under the MNOS memory gate MG increases. Therefore, MNOS memory gate MG
And the potential difference between the tunnel insulating film and the SiO ₂ film 55 becomes large, and even with a small amount of incident light, tunnel injection of charges into the SiO ₂ film 55 occurs and writing can be performed in a short time. However, if the preset voltage V _SO is lowered too much, the bias charge amount E1 increases too much, and the flat band voltage V _FB changes greatly despite the increase or decrease in the optical signal charge amount E2. This must be taken into consideration because the range of E2 will be reduced.

FIG. 9 is a potential distribution diagram for explaining the detection operation from the image memory shown in FIG. 7, particularly the n ⁺ diffusion layer 52, the substrate surface under the memory gate MG, and the surface substrate under the transfer gate TG. And n ⁺ diffusion layer The potential distribution of the diffusion layer 53 is shown. The reading principle will be described below with reference to FIG. Incidentally, in reading, the substrate surface potential under the transfer gate TG phi _TG, in the maximum level of the substrate surface potential when the scan pulse is applied to the MNOS memory gate MG of the transistor T2 phi _MG1
A voltage is applied to the transfer gut TG of the transistor T3 so as to be higher than the voltage.

First, in the MNOS memory gate MG of the memory transistor T2 in each pixel 46, by the horizontal scanning circuit 41, the Al horizontal scanning line l2
A horizontal scanning pulse is sequentially applied via. Then, the potential of the n ⁺ diffusion layer 52 which is the source of the transistor T1 is V _S , and when the voltage applied to the n ⁺ diffusion layer 54 which is the drain-in of the transistor T3 is sufficiently large, as shown in FIG. It is fixed at φ _MG1 in the substrate surface potential under the gate MG. Note that φ _MG1 represents the substrate surface potential under the MNOS memory gate MG in the erased state, that is, the 0 written state as analog information, and φ _MG2 represents the substrate surface potential under the MNOS memory gate MG in the written state of optical signal charges. The read operation at the substrate surface potential φ _MG1 will be described below. At this time, the voltage applied to the MNOS memory gate MG is sufficiently small so that writing does not occur.

When the scanning pulse to the memory gate MG ends, the n ⁺ diffusion layer 52 which is the source of the transistor T1 is reverse biased,
A potential well is formed as shown in FIG. The depth of this potential well is determined by the substrate surface potential φ _MG1 under the MNOS memory gate MG when the scan pulse is applied.

Then, the overflow gate OG of the transistor T1 is turned on by applying a predetermined voltage from the overflow gate terminal P _{OG at} a time corresponding to each blanking period of horizontal scanning,
By supplying a predetermined voltage from the overflow drain terminal P _OD to the n ⁺ diffusion layer 51 which is the drain of the transistor T1, the source of the transistor T1 and the photodiode PD are also formed as shown in FIG. Injecting charges into the existing n ⁺ diffusion layer 52.

After that, a scan pulse is sequentially applied to the MNOS memory gate MG of the memory transistor T2 of each pixel 46, and the accumulated charge is transferred beyond the substrate surface potential φ _MG1 level of the MNOS memory gate MG as shown in FIG. N ⁺ diffusion layer via gate TG
Transferred to 54. That is, as the substrate surface potential φ _MG1 is lower, a smaller amount of charges are transferred to the n ⁺ diffusion layer 54.
The charges transferred to the n ⁺ diffusion layer 54 are output as a video output v _OUT via the Al vertical signal line l3, the transistor 44, and the integrating circuit 45. That is, the stored contents of the MNOS memory gate MG can be read out as analog information from the video output V _OUT .
In this operation, when MNOS memory gate MG is turned on, n ⁺
The amount of charge flowing from the diffusion layer 52 to the n ⁺ diffusion layer 54 becomes smaller as the substrate surface potential φ _MG under the MNOS memory gate MG becomes smaller.
Further, since the substrate surface potential φ _MG has a negative correlation with the flat band voltage V _FB as described above, the larger the flat band voltage V _{FB, the} smaller the amount of charges flowing to the n ⁺ diffusion layer diffusion layer 54. Therefore, the larger the amount of charges accumulated in the MNOS memory gate MG during writing, that is, the larger the amount of optical signal charges E2, the smaller the video output V _OUT during reading.

On the other hand, in order to erase the information stored in the memory transistor T2, the memory gate MG of the memory transistor T2 of all the pixels 46 is used.
A large negative erase pulse voltage to the
A flat band voltage is generated by tunneling charges from the O ₂ film 55.
This is done by lowering V _FB . This erase operation returns the flat band voltage V _FB to the initial state.

Next, the imaging operation will be described. First, a constant voltage is applied to the transfer gates TG of the transistors T3 of all the pixels 46, and MN of the memory transistor T2 is supplied with a small voltage that does not cause writing.
The ONS memory gate MG is periodically turned on, and the optical signal charges accumulated in the n ⁺ diffusion layer 52 are output from the n ⁺ diffusion layer 54 as a video output V _OUT . At this time, assuming that the potential of the n ⁺ diffusion layer 54 is V _D , it is necessary to set φ _MG <V _D and φ _MG <V _TG . This is MN
Flat band voltage V _FB stored in OS memory gate MG
This is because the difference in the substrate surface potential φ _MG due to the displacement of does not affect the video output V _OUT .

[Problems to be Solved by the Invention]

The conventional image memory device is configured as described above,
In the configuration for directly storing analog optical information as shown in FIG. 7, since the photoelectric conversion unit, the storage unit and the scanning circuit are provided on the same plane, the aperture ratio is limited and the photoelectric conversion sensitivity is deteriorated. was there.

Also, if a solid-state image sensor as shown in FIG. 6 is used, the aperture ratio will be 100%, but since the optical signal charge amount is A / D converted and stored in the memory as a digital signal, as described above.
A / D converter is required separately and the configuration becomes complicated. Further, there is a problem that the processing speed becomes slow because the amount of light signal charge is once changed to a time series signal and then A / D converted and stored in the memory.

The present invention has been made to solve the above problems, the optical signal charge can be stored in the memory as analog information without using an A / D converter, and the photoelectric conversion sensitivity is improved. The purpose is to obtain an image memory device.

[Means for Solving the Problems]

The image memory device according to the present invention has a first layer having a photoelectric conversion part having an aperture ratio of 100% and a transistor characteristic formed according to the amount of charges formed under the first layer and converted by the photoelectric conversion part. Change, and a second layer having a memory transistor for analog-storing the charge amount in the previous pixel collectively is provided, and the first layer and the second layer are electrically connected directly.

[Action]

Since the first layer in the present invention has the photoelectric conversion part having an aperture ratio of 100%, the light conversion sensitivity can be greatly improved.

〔Example〕

FIG. 1 shows an image memory device 1 according to an embodiment of the present invention.
It is sectional drawing which shows a pixel part. The basic structure of this image memory device is almost the same as that shown in FIG. However, the photodiode PD is not used as the photoelectric conversion means, but the amorphous Si: H film 31 is used.

As shown in the figure, an image memory including the MNOS memory gate MG shown in FIG. 7 is formed in the lower layer LD, and photoelectric conversion including the amorphous Si: H film 31 shown in FIG. 6 is formed in the upper layer LU. Forming a part. Then, the Al layer 60 is formed between the Al layer 27 and the n ⁺ diffusion layer 52 by penetrating the SiO ₂ film 55 and the Si ₃ N ₄ film 56, and the amorphous Si: H film 31 and the n ⁺ diffusion layer 52 are formed. Electrical connection is being made. Further, other regions between the upper layer portion LU and the lower layer portion LD are insulated by the interlayer insulating film 61 made of polyimide or the like.
The interlayer insulating film 61 also has a role of flattening the lower layer LD. In addition, regarding other configurations, the sixth example shown in the conventional example is used.
The description is omitted because it is the same as that shown in FIG.

With this configuration, the upper layer LU formed on the entire surface
Amorphous Si: based on the amount of charge photoelectrically converted by H film 31, flood-band voltage MNOS memory gate MG V _FB
By changing the, the analog storage of optical information can be performed. As a result, it is possible to obtain an image memory device that does not require an A / D conversion unit while maintaining an aperture ratio of 100%. Therefore, by using this memory element, it is possible to obtain a high-performance and highly integrated three-dimensional image processor. The writing, reading, and imaging operations in this image memory device are the same as those in the image memory device shown in FIG. 7, except that the high-electric conversion means is changed from the photodiode to the amorphous Si: H film.

In this embodiment, as the non-volatile transistor,
The MNOS structure consisting of Si ₃ N ₄ film is shown, but floating gate MOSFET structure, MONOS (Metal Oxide Nitride)
Other non-volatile transistors such as Oxitde Semiconductor) may be used. That is, the transistor characteristics such as the flat band voltage V _FB change according to the high signal charge amount, so that a transistor capable of analogly storing the optical signal charge amount can be used instead.

In addition, although an amorphous Si: H film is shown as the photoelectric conversion means in this example, other photoelectric conversion films such as a Nubicon film (Zn _1-x Cd _x Te) may be used.

〔The invention's effect〕

As described above, according to the present invention, since the photoelectric conversion portion of the first layer has an aperture ratio of 100%, photoelectric conversion sensitivity can be greatly improved and photoelectric conversion can be performed.

In addition, the memory transistor formed in the second layer which is electrically directly connected to the first layer has transistor characteristics that are changed depending on the amount of charge photoelectrically converted by the photoelectric conversion portion of the first layer. Therefore, it is not necessary to separately provide an A / D conversion unit because the charge amount is stored in analog storage for all pixels collectively.

[Brief description of drawings]

FIG. 1 is a sectional view showing an image memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional image processor, and FIG. 3 is a block configuration of the image processor shown in FIG. FIGS. 4 (a) and 4 (b) are cross-sectional views showing a conventional photoelectric conversion circuit and its equivalent circuit diagram, and FIG. 5 is a circuit configuration diagram showing a conventional solid-state imaging device having a laminated structure, and FIG. Is a sectional view showing a conventional photoelectric conversion circuit, FIGS. 7A and 7B are circuit configuration diagrams showing a basic configuration of a conventional image memory device, and sectional views showing a sectional structure of one pixel thereof, FIG. 9 (a) to 9 (e) are schematic diagrams of potential distributions showing the write operation of the image memory device shown in FIG. 7, and FIG.
7A to 7D are schematic diagrams of potential distributions showing the read operation of the image memory element shown in FIG. In the figure, 31 is an amorphous Si: H film, 27 and 60 are Al layers, 5
1 to 54 are n ⁺ diffusion layers, MG is MNOS memory gate, 55 is SiO
_{The two} films and 56 are Si ₃ N ₄ films. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 27/148 29/788 29/792 H04N 5/335 U

Claims (1)

[Claims] 1. A first layer having a photoelectric conversion part having an aperture ratio of 100%, and transistor characteristics which are formed under the first layer and change according to the amount of charges converted by the photoelectric conversion part. And a second layer having a memory transistor for analog-storing the charge amount for all pixels collectively, and the first layer and the second layer are electrically connected directly.