JPH05244513A - Photoelectric converter and its drive method - Google Patents

Abstract

PURPOSE:To prevent fluctuation in a light shield picture element output and crosstalk caused by a carrier generated in a valid picture element region leaked to the light shield picture element in the photoelectric converter having light shield picture elements and valid picture elements. CONSTITUTION:The photoelectric converter and its drive method is provided with a 2nd light shield picture element having a light shield picture element and a valid picture element and a p-n junction provided between the light shield picture element and the valid picture element, a wiring 15 connecting to a semiconductor layer (base 1) on the front side o the p-n junction and a means applying a reverse bias to the p-n junction via the wiring 15 during the storage period of the photoelectric converter and applying a reset voltage during the reset period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an all-pixel collective reset type photoelectric conversion device having light-shielding pixels and effective pixels.

[0002]

2. Description of the Related Art Conventional BASIS (BAse Store)
FIG. 10 is a plan view of the ed Image Sensor) area sensor. 11 is a sectional view taken along line XX ′ in FIG.
Shown in. In FIGS. 10 and 11, 1 is a P-type impurity region which is a base of a bipolar transistor, 2 is an n ⁺ region which is an emitter, 3 is an Al wiring which is an emitter output line,
4 is a poly-Si electrode which is a gate electrode, 5 is a capacitor C
_OX , 6 is an element isolation region, 7 is an Al film as a light-shielding film, 8 is an n ^- epitaxial layer, 9 is a semiconductor substrate Si, 1
0 is a collector electrode, 11 is a gate oxide film, 12 is an interlayer insulating film 1, 13 is an interlayer insulating film 2, 14 is a surface protective film, 15
Is a light-shielding film.

Next, the basic operation of the BASIS area sensor will be briefly described. The BASIS operation consists of three operations: (1) storage operation, (2) read operation, and (3) reset operation.

(1) Storage Operation The storage operation starts when the reset operation is completed and the base and emitter of the bipolar transistor are reversely biased. The base potential increases as holes generated by incident light are accumulated in the base 3 in the base region 3 and the depletion layer between the base and the collector.

The signal V _P due to the holes is expressed by the following equation.

V _P = i _P · t _S / C _B where i _P is the photocurrent, t _S is the storage time, and C _B is the base capacitance.

(2) Read Operation A positive pulse is applied to C _OX 5 through the horizontal drive line. When the base potential is raised in the positive direction by capacitive coupling through C _OX 5 and the base-emitter is forward biased, a read operation is performed.

(3) Reset Operation The reset of BASIS consists of a combination of two operations.

First, in the first reset, a negative pulse is applied to the p-MOS gate electrode 4 through the horizontal drive line. Thereby, the p-MOS is turned on and the base 3 is grounded.

Next, in the second reset, the emitter output line 3
_Is grounded and a positive pulse is applied to C _OX 5. The base 1 is raised to a positive potential, a forward bias is applied between the base and emitter, and the recombination of electrons and holes lowers the base potential. When the pulse applied to C _OX 5 returns to GND, a reverse bias state is returned between the base and emitter, and the reset operation ends.

As shown in FIG. 10, a reset p-MOS is provided.
Are formed in the separation area of each pixel. When the p-MOS gate 4 is turned on, the bases 3 of the adjacent pixels are turned on and resetting is performed. On the other hand, when gate 4 is OFF, p
-MOS plays a role as a pixel separation region. Referring to FIG. 11, the p-MOS gate 4 is shielded from light by the vertical output line 3. Therefore, the BASIS area sensor can obtain a high aperture ratio.

Further, since the first light-shielding pixel is covered with the light-shielding layer 7, light does not enter the base 1, the base potential becomes constant regardless of the light quantity, and the light-shielding pixel output potential is set as the reference potential. Used.

FIG. 12 is a schematic circuit diagram of a conventional solid-state image pickup device using such a photoelectric conversion element.

The electrodes 4 of the elements in each line are commonly connected to the horizontal lines HL _{1 to} HL _m , respectively, and connected to the terminal 20 via the switches SW _{1 to} SW _m , respectively. The pulse φd is input to the terminal 20.

The switches SW _{1 to} SW _m are analog switches composed of nMOS transistors. The output terminals of the vertical scanning circuit 21 are connected to their gate terminals and controlled by their output pulses φv _{1 to} φv _m .

The emitter electrodes 3 of each element are connected to the vertical lines VL _{1 to} VL _n column by column. Vertical line VL
_{1 ~VL n} is grounded via a reset transistor Qb ₁ ~Qb _n, pulse φr is input to the gate electrode of the transistor Qb ₁ ~Qb _n.

Further, the vertical line VL ₁ ~VL _n, is connected to each storage capacitor C ₁ -C _n via the transistor Qa ₁ ~Qa _n, further capacitors C ₁ -C _n transistor Q ₁ to Q _n Is connected to the output line 22 via.

[0018] The pulse φt is commonly input to the gate electrode of the transistor Qa ₁ ~Qa _n, transistor Q ₁ ~Q
_A pulse φh ₁ from the horizontal scanning circuit 23 is applied to the gate electrode of _n.
~ Φh _n are input respectively.

The output line 22 is grounded via the transistor Qrh and connected to the input terminal of the amplifier 24. The pulse φrh is input to the gate electrode of the transistor Qrh.

The constant potential V _c for setting the base potential of each element is the ground potential.

Next, the operation will be described with reference to the timing chart of FIG.

First, only the pulse φv ₁ of the vertical scanning circuit 21 is set to the high level, and the switch SW ₁ is turned on. Also, the ON state of the transistor Qa ₁ ~Qa _n by a pulse φt to the high level.

Next, when the pulse φd is set to a positive potential for the period T ₁ , the element S _{11 of} the first line is passed through the switch SW ₁ .
A positive voltage is applied to the electrodes 4 of S _1n . As a result, the read operation of the first line is performed, and the read signals of the first line are the vertical lines VL _{1 to} VL _n and the transistors Qa ₁ to.
They are respectively stored in the capacitor C ₁ -C _n through qa _n.

Next, the pulse φt goes low, turning off the transistors Qa ₁ -Qa _n . The pulse φh ₁ ~φh _n are sequentially output from the horizontal scanning circuit 21, the read signal stored in the capacitor C ₁ -C _n is fetched sequentially to the output line 22 via the transistor Q ₁ to Q _n accordingly, Output signal V through amplifier 24
is output to the outside to the serial as _out. Note that the pulse φrh rises every time each read signal is output, turning on the transistor Qrh to remove the carrier on the output line 22.

When the operation of the first line is completed in this way,
The pulse φv ₁ falls, and the switch SW ₁ is turned off. Then, the pulse φt ₁ rises and the transistor Q
and turn on the a ₁ ~Qa _n. As a result, the carriers remaining in the capacitors C _{1 to} C _n are transferred to the vertical line V.
L ₁ is removed through ～VL _n and transistor Qb ₁ ~Qb _n.

Thereafter, the same operation is performed for each line, and the second
~ The read signal of the m-th line is sequentially output.

[0027]

However, in the above-mentioned conventional example, the carriers generated in the effective pixel area leak into the light-shielding pixel, so that the light-shielding pixel output fluctuates during light irradiation and crosstalk increases. There was a drawback that it would end up.

[0028]

In order to solve the above-mentioned problems, the present invention has a light-shielding pixel and an effective pixel,
A photoelectric conversion device comprising: a second light-shielding pixel having a pn junction provided between the light-shielding pixel and the effective pixel; and a wiring connected to the semiconductor layer on the front surface side of the pn junction.
And a reverse bias is applied to the pn junction through the wiring during the accumulation period of the photoelectric conversion device, and a reset voltage is applied or floated during the reset period. The driving method of the converter is used as a means.

According to the present invention, a second light-shielding pixel having a pn junction, which is separated from an adjacent pixel by a p-MOS, is provided between the first light-shielding pixel and the effective pixel, and all the pixels are collectively reset. Depending on the driving method, a reverse bias is applied to the pn junction during the accumulation period, and a reset voltage is applied to the p region during the reset period, or a floating voltage is applied to the p region so that the reset time is not increased and the first light-shielded pixel is applied. This prevents the unnecessary carriers from leaking in and reduces crosstalk.

[0030]

[Embodiment 1] FIG. 1 shows a sectional view of a BASIS area sensor according to a first embodiment of the present invention. Here, the same parts as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted. 15 is the second
The wiring is connected to the base region 1 of the light-shielded pixel.

During the accumulation period of the sensor, a voltage is applied between the base collectors of the second light-shielding pixels (hereinafter referred to as dummy pixels) so as to be in a reverse bias state, so that the effective pixels are transferred to the first light-shielding pixels. It is possible to absorb unnecessary carriers that leak. Further, by applying the first reset potential to the wiring 15 in the first reset period, the base region 1 of the OB pixel can be used as the first reset power supply.

Here, the carrier absorption of the dummy pixel will be briefly described. When the pn junction of the dummy pixel is a step junction, the depletion layer width W formed in the p base n type collector region
Is

[0033]

It is given by Here, N _A is the base impurity concentration, N _D is the collector impurity concentration, ε _s is the dielectric constant, q is the elementary charge, and V _BC is the base collector voltage (forward bias and positive sign). V _bi is called the built-in potential,

[0034]

It is given by Where k is Boltzmann's constant and n
_i is the intrinsic carrier concentration.

When unnecessary carriers diffuse from the effective pixel into the depletion layer region, holes are absorbed by the base and electrons are absorbed by the collector by the electric field in the depletion layer.

It can be seen from the equation (1) that the depletion layer width W increases when V _BC is reverse biased (the base is negative and the collector is positive potential).

Therefore, in order to efficiently absorb the unnecessary carriers in the dummy pixel, it is necessary to apply a negative potential to the base to widen the depletion layer.

FIG. 2 is a schematic circuit diagram of a photoelectric conversion device according to the present invention. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. Qc in FIG. 2 ₁ ~Qc _n is MOS reset
Transistors are connected to the vertical lines VL _{1 to} VL _n , respectively. Reset voltage V _VC is applied to Qc ₁ ~Qc _n is turned ON vertical line.

Next, the driving method will be described with reference to the timing charts of FIGS. A feature of the driving method of the present embodiment is that after the resetting of all the elements, the storage period starts. FIG. 3 is a timing chart of the reset and accumulation period.

During the T ₅ period, φ _{BR is set} to the low level and p
-Turn on the MOS transistor. When the p-MOS transistor is turned on, a positive reset voltage V _C (≈3V) is applied to the source potential of the p-MOS transistor of the element, the p-MOS transistor becomes conductive and the base region 3 is reset to the positive potential. .

In the period T ₅ , φb is set to the reset voltage V _C, and the p base region of the dummy pixel functions as a reset power supply. As a result, the reset period can be shortened as compared with the conventional case.

After resetting the base potentials of all the elements, resetting is performed to set the base potentials to GND during the T ₆ period. By the [phi] r ₁ to High to T ₆ period, the n-MOS transistor Qc ₁ ~Qc _n is ON, the application of a negative voltage V _VC (-1~-2V) to the emitter of the respective elements. At this time, electrons are injected from the emitter to the base, and the base potential drops to the GND level. By this reset, the base potentials of all the elements are set to the GND level.

After resetting all the pixels as described above, reset for setting the base potential to the reverse bias state is performed for each 1H (horizontal) line.

During the period T ₇ , φr ₂ is set to the high level, and the emitter of the element is grounded to GND. First, φv ₁ and φd are set to High, and the elements S _{11 to} S of the first H line are set.
The base potential of _1n is raised by capacitive coupling. At this time, since the emitters are grounded, the base potentials of the elements S _{11 to} S _1n decrease with time. After that, set φd to Low
It is returned to the level and the base potential is returned to the initial reverse bias state.

This completes the resetting of the first H line,
The resetting from the second H line onward is similarly performed.

After the reset operation is completed, the accumulation period starts. During this period, φb is set to −V _D so that the base-collector is reverse-biased to have an unnecessary carrier absorption function.

After the accumulation period ends, the signal is read.
The read operation is performed in the same manner as the method described in the conventional example.

The above-described method of resetting all the elements at once can be used for still image photographing of an SV camera or the like.

As described in the present embodiment, the wiring is connected to the base region of the dummy pixel to apply a voltage such that the base-collector is reversely biased during the accumulation period, and the reset voltage is applied during the reset period. Depending on the circuit configuration and timing, the crosstalk between the effective pixel and the light-shielded pixel can be reduced and the reset time can be shortened.

[Embodiment 2] FIG. 5 shows a circuit diagram of a second embodiment of the present invention. A timing chart is shown in FIG. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In FIG. 5, Qd is an n-MOS transistor, which is connected to the vertical line 15 of the dummy pixel.

Φc is a pulse applied to the gate of the n-MOS transistor Qd. φc is Hi during the accumulation period
The level becomes gh and the voltage V _D is applied to the vertical line 15, and the base of the dummy pixel is fixed at V _D. Normally, V _D is set to a value such that the base and collector are reversely biased.

Further, during the period T _{5 in} which the base potential of the element is reset, φc becomes Low level, and the base of the dummy pixel is in the floating state like the effective pixel.

The present embodiment is characterized in that the base of the dummy pixel becomes floating during the base reset period T ₅ .

Since the base of the dummy pixel is reset in the same manner as the effective pixel, it is possible to suppress the crosstalk between the light-shielded pixel and the effective pixel in the same reset time as the conventional one.

[Embodiment 3] FIG. 7 shows a schematic sectional view of a third embodiment of the present invention. In the first and second embodiments, the dummy pixel is only one pixel between the effective pixel and the light-shielding pixel, but in this embodiment, two pixels are set as the second light-shielding pixel (dummy pixel) as shown in FIG. 7, for example. , Provided on a plurality of pixels. With this configuration, it is possible to further reduce crosstalk.

[Embodiment 4] FIG. 8 shows a sectional view of a fourth embodiment of the present invention.

In the first to third embodiments, the wiring 15 is directly connected to the base of the dummy pixel, but in the present embodiment, it is connected to the emitter 2 like other pixels. Φb is set so that the base-collector is reversely biased during the accumulation period. Unwanted carriers that diffuse from the effective pixel to the light-shielded pixel are absorbed by the base 1 of the dummy pixel, and are recombined with the electrons supplied from the emitter 2 to disappear.

The device of this embodiment can be applied to the circuit of FIG. 2 or 5 as it is.

[Embodiment 5] FIG. 9 shows a sectional view of a fifth embodiment of the present invention.

This embodiment is characterized in that a plurality of dummy pixels of Embodiment 4 are provided. In the case of this configuration, the fourth embodiment
The above crosstalk can be reduced.

[0061]

As described above, the second light-shielding pixel having the pn junction separated from the adjacent pixel by the p-MOS is provided between the first light-shielding pixel and the effective pixel, and p
By applying a reverse bias to the n-junction and applying or floating the reset voltage to the p region during the reset period, crosstalk can be reduced without increasing the reset time.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of the present invention.

FIG. 3 is a timing diagram of the first embodiment of the present invention.

FIG. 4 is a timing diagram of the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a second embodiment of the present invention.

FIG. 6 is a timing diagram of the second embodiment of the present invention.

FIG. 7 is a sectional view of a third embodiment of the present invention.

FIG. 8 is a sectional view of a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a fifth embodiment of the present invention.

FIG. 10 is a plan view of a conventional BASIS area sensor.

FIG. 11 is a sectional view of a conventional BASIS area sensor.

FIG. 12: Conventional BASIS area sensor circuit diagram

FIG. 13: Timing chart of conventional BASIS area sensor

[Explanation of symbols]

1 P-type base region 2 n ⁺ type emitter region 3 Emitter output line 4 Gate electrode 5 Capacitor 6 Element isolation region 7 Light-shielding film 8 n ^- Epitaxial layer 9 Semiconductor substrate 10 Collector electrode 11 Gate oxide film 12 Interlayer insulating film 1 13 Interlayer insulation Film 2 14 Surface protection film 15 Dummy pixel vertical wiring

Claims (6)

[Claims] 1. A second pixel having a light-shielding pixel and an effective pixel, and a pn junction provided between the light-shielding pixel and the effective pixel.
And a wiring connected to the semiconductor layer on the surface side of the pn junction, and a reverse bias is applied to the pn junction via the wiring during the accumulation period of the photoelectric conversion device. A photoelectric conversion device comprising means for applying a reset voltage during a reset period. 2. The photoelectric conversion device according to claim 1, wherein the wiring is connected to a base of a transistor forming the second light-shielding pixel. 3. The photoelectric conversion device according to claim 1, wherein the wiring is connected to an emitter of a transistor forming the second light-shielding pixel. 4. The photoelectric conversion device according to claim 1, wherein the second light-shielding pixel is provided over a plurality of pixels. 5. A second pixel having a light-shielding pixel and an effective pixel, and a pn junction provided between the light-shielding pixel and the effective pixel.
A light-shielding pixel and a wiring connected to the semiconductor layer on the front surface side of the pn junction, the photoelectric conversion device having the p-type via the wiring during an accumulation period of the photoelectric conversion device. A method for driving a photoelectric conversion device, characterized in that a reverse bias is applied to the -n junction and a reset voltage is applied during a reset period. 6. The method of driving a photoelectric conversion device according to claim 5, wherein the P layer is made floating during the reset period.