JP4604751B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state imaging device that obtains an image signal by photoelectrically converting a formed image of a subject, and particularly relates to prevention of blooming of a reproduced image.

  Conventionally, a solid-state imaging device, for example, a CCD solid-state imaging device, includes a light-shielding dummy pixel that can obtain an optical black level (so-called optical black: OPB) outside an effective pixel region (light receiving portion). This is because the dark current is subtracted from the signal. The light-shielding dummy pixel is shielded by the Al film and does not feel light, but is configured to generate the same dark current as the effective pixel. A signal is output from the light receiving unit as a reference level. This prevents the signal level of the light receiving unit from fluctuating due to temperature changes. However, when strong light enters the vicinity of the OPB pixel of the light receiving unit, the charge overflows from the pixel of the light receiving unit, and this charge flows into the OPB pixel, resulting in a high black level, resulting in deterioration in the quality of the reproduced image ( Patent Document 1).

  FIG. 8 is a diagram for explaining the flow of charges from the light receiving portion to the OPB portion. When strong light strikes the light receiving pixel in the lower right of the figure, the charge generated by photoelectric conversion by this light receiving pixel overflows, and this charge is a broken line in the upper pixel, upper left pixel, and left pixel that are the surrounding OPB pixels. Flow as shown in. The overflowing charge also flows to the substrate portion as indicated by a broken line 60.

  In order to prevent this, a solid-state imaging device having a structure that prevents charge from flowing into the OPB portion is known. This is because an N-type layer that is reverse-biased between the OPB pixel and the effective pixel sandwiches the charge that is about to flow into the OPB pixel, so that the charge overflowing from the effective pixel is transferred to the OPB pixel. It is blocking the flow. However, this configuration is effective only when an N-type semiconductor substrate is used. Even when applied to a CMOS solid-state imaging device that generally uses a P-type substrate, the charge generated at a deep location on the substrate is not affected. Has no effect. Further, since the N-type layer to which reverse bias is applied is separated from the N-type semiconductor substrate, the charge trapping effect is insufficient.

Therefore, in the CMOS type solid-state imaging device, the light receiving portion and the OPB portion (light-shielding portion) are formed , and the N-type layer that reaches the substrate position deeper than the light receiving portion and the OPB portion and is reversely biased is formed as the light receiving portion. When the strong light is incident on the light receiving portion, the charge leaked from the light receiving portion (especially the charge generated in a deep place on the substrate) is caused by the action of the N-type layer. The thing of the structure which prevents flowing into a part is known (refer patent document 2).
JP 10-12857 A (Page 3, Fig. 1) JP 2002-329854 A (3rd page, FIG. 2)

In the configuration capable of preventing the so-called blooming by preventing the flow of charge from the light receiving portion to the OPB portion of the above CMOS type solid-state imaging device, pixels arranged in the OPB portion (hereinafter referred to as OPB pixels). There is a problem that the chip size is increased due to the structure in which the N-type layer is formed between the effective pixels arranged in the light receiving portion (hereinafter referred to as light receiving portion pixels).

  The present invention has been devised in view of the above circumstances, and the object of the present invention can be applied to a CMOS solid-state imaging device without increasing the chip size, and the flow of charge from the light receiving portion to the OPB portion can be prevented. An object of the present invention is to provide a solid-state imaging device that can be sufficiently prevented.

In order to achieve the above object, the present invention provides a semiconductor substrate, a light receiving portion that is formed on the semiconductor substrate and that arranges pixels that photoelectrically convert incident light and accumulates charges, and is formed on the semiconductor substrate to block light. A photoelectric conversion unit comprising the light shielding unit for arranging the pixels, and an unquestioned region unit for arranging dummy pixels, which is formed between the light receiving unit and the light shielding unit on the semiconductor substrate, and A readout unit that reads out the electric charge photoelectrically converted by the photoelectric conversion unit and a power supply line unit that supplies operation power to the pixel are always connected electrically, and further on the surface of the semiconductor substrate in the dummy pixel. Are provided with a transfer gate for controlling transfer of charges obtained by photoelectric conversion by the photoelectric conversion unit, and a reset gate for resetting the reading unit. DOO and the reset gate to a predetermined voltage, characterized in that it is always applied.

As described above, in the present invention, the photoelectric conversion unit, the reading unit, and the power supply line unit that constitute the dummy pixels arranged in the unquestioned region are always electrically connected, so that the pixels in the unquestioned region are substantially connected. By using a reverse-biased N-type region, the charge that flows from the light-receiving unit pixel to the OPB pixel can be captured by the reverse-biased N-type region in the unquestioned region. Thus, Ru can be sufficiently prevented blooming CMOS type solid-state imaging device.

According to the present invention, the photoelectric conversion unit, the reading unit, and the power supply line unit that constitute the dummy pixels arranged in the unquestioned region are always electrically connected without increasing the chip size. The present invention can be applied to a CMOS type solid-state imaging device and can sufficiently prevent the flow of charges from the light receiving portion to the OPB portion. Therefore, even when strong light is incident on the light receiving unit, it is possible to obtain a stable black level, and it is possible to prevent image deterioration due to black level fluctuations.

  It can be applied to a CMOS solid-state imaging device without increasing the chip size, and the purpose of sufficiently preventing the flow of charge from the light receiving portion to the OPB portion is predetermined for the transfer gate and reset gate of the pixels arranged in the unquestioned region. Supply the operating power of the readout unit and the pixel by applying voltage constantly or between the photoelectric conversion unit of the pixel in the unquestioned region and the readout unit that reads out the photoelectric conversion by this photoelectric conversion unit By connecting the power supply line section to the power supply line section with a conductive region, or by forming either or both of the photoelectric conversion section and the readout section forming the pixels in the unquestioned region directly on the semiconductor substrate, the photoelectric conversion section This is realized by electrically connecting the lower part of either one or both of the readout portion and the semiconductor substrate to the semiconductor substrate.

  FIG. 1 is a schematic plan view of a solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device of the present embodiment is, for example, a CMOS image sensor. An OPB unit 32 surrounds the light receiving unit 31, and an unquestionable region 33 is formed between the light receiving unit 31 and the OPB unit 32 by arranging dummy pixels. The pixels forming the light receiving unit 31, the OPB unit 32, and the unquestioned region 33 have the same configuration.

  FIG. 2 is a partial cross-sectional view of the unquestioned region 33 shown in FIG. In a P-type well region 41 formed on the N-type silicon substrate 40, a photodiode part (PD) 42 which is a photoelectric conversion part, and a floating diffusion part (FD) 43 for reading out charges generated in the photodiode part 42. A power line portion 44 for supplying power to the circuit portion or the like as shown in FIG. 3 is formed, and an insulating film (not shown) is provided on the photodiode portion 42, the floating diffusion portion 43, and the power line portion 44. A reset gate 45 and a transfer gate 46 are formed.

  FIG. 3 is an example of a circuit diagram illustrating a circuit configuration of the light receiving unit 31. Each pixel arranged in the light receiving unit 31 is composed of one photoelectric conversion element and a plurality of transistors, and all have the same circuit configuration. The pixel is connected to the photoelectric conversion element 1 via the transfer transistor 3 and to the amplification transistor 2, and a connection point between the transfer transistor 3 and the transistor 2 is connected to a reset transistor 4 for resetting the gate electrode potential. Yes. The output of the transistor 2 is connected to a pixel output line 7 via a selection transistor 6 for selecting an output pixel. A transistor 8 for supplying a constant current to the pixel output line is connected to the pixel output line 7. The drains of the reset transistor 4 and the amplifying transistor 2 are both connected to the power supply potential supply line 5. The transistor 8 supplies a constant current to the amplifying transistor 2 of the selected pixel to operate the amplifying transistor 2 as a source follower, and a potential having a certain voltage difference from the gate potential of the amplifying transistor 2 is output to the pixel. Appears on line 7.

  9 is a transfer signal wiring for controlling the gate potential of the transfer transistor 3, 10 is a reset signal wiring for controlling the gate potential of the reset transistor 4, and 11 is a selection for controlling the gate potential of the selection transistor 6. A signal line 12 is a constant potential supply line for supplying a constant potential to the gate so that the transistor 8 operates in a saturation region to supply a certain current. A pulse terminal 13 supplies a transfer pulse to the transfer signal wiring of each row, and is connected to the input terminal of the row selection AND element 14. An output from the vertical selection means 15 is connected to the other input terminal of the row selection AND element 14, and an output terminal of the row selection AND element 14 is connected to the transfer signal wiring 9. Reference numeral 16 denotes a pulse terminal for supplying a reset pulse to the reset signal wiring of each row, which is connected to the input terminal of the row selection AND element 17. An output from the vertical selection means 15 is connected to the other input terminal of the row selection AND element 17, and an output terminal of the AND element 17 is connected to the reset signal wiring 10. Reference numeral 18 denotes a pulse terminal for supplying a selection pulse to the selection signal wiring 11 of each row, which is connected to the input terminal of the row selection AND element 19. The other input terminal of the row selection AND element 19 is connected to the output from the vertical selection means 15, and the output terminal of the row selection AND element 19 is connected to the selection signal line 11. With such a configuration, each control pulse is supplied only to each signal wiring of the pixels constituting the row selected by the vertical selection unit 15, and the light reception signal (pixel signal) of each pixel is read onto the pixel output line 7. It is. The column selection means 21 selects a column among the pixel signals read from a certain row, and the pixel signal on the pixel output line 7 of the selected column passes through the CDS circuit 20 that reduces sampling noise and is not shown. By outputting to the AGC circuit, pixel signals from each pixel of the light receiving unit 31 are sequentially read out. The power supply potential supply line 5 corresponds to the power supply line portion 44 in FIG.

  Next, the operation of the unquestioned area shown in FIG. 2 will be described. The reset gate 45 and the transfer gate 46 forming the pixels arranged in the unquestioned region have the same potential as the DC power source or the potential of the selection signal wiring over the entire period during which the CMOS image sensor is operating. A predetermined voltage of the same potential is constantly applied and turned on. For this reason, as shown in FIG. 2, a channel is formed between the photodiode portion 42 and the floating diffusion portion 43, and between the floating diffusion portion 43 and the power supply line portion 44. The photodiode portion 42 and the floating diffusion portion 43 are Connected to the power line 44, each pixel in the unquestioned region 33 is substantially an N-type layer that is reverse-biased. For this reason, the periphery of the light receiving portion 31 is surrounded by a reverse-biased N-type layer, and the charge that flows from the light-receiving portion 31 to the OPB portion 32 is captured by the reverse-biased N-type layer. , The OPB unit 32 cannot be reached. In FIG. 1, the charge overflowing from the light receiving unit 31 is blocked by the unquestioned region 33 as indicated by 50 and does not flow into the OPB unit 32.

Here, for example, the transfer gate of the pixel of the light receiving unit 31 is connected to the transfer transistor 3 of FIG. 3, it is necessary to directly connect the connection destinations of the wiring corresponding to the transfer signal wiring 9 and the reset signal wiring 10 shown in FIG. 3 to the power supply voltage. Therefore, the continuity of the pixel arrangement between the OPB pixel and the light receiving unit pixel is not impaired at all.

  According to the present embodiment, a predetermined voltage is always applied to the reset gate 45 and the transfer gate 46 of the pixels arranged in the unquestionable region 33 between the light receiving unit 31 and the OPB unit 32, thereby substantially substituting the pixels in the unquestionable region 33. By using the N-type layer reversely biased in this way, the charge that flows from the light-receiving unit pixel to the OPB pixel is captured by this reverse-biased N-type layer and discharged through the power supply line unit 44. Can be prevented. In addition, since the reverse-biased N-type layer is generated in the pixels in the unquestioned region 33 originally between the light receiving unit 31 and the OPB unit 32, the continuity between the OPB pixel and the light receiving unit pixel is not impaired at all. The above effects can be obtained without increasing the chip size. Further, since the unquestionable region 33 has a width corresponding to a plurality of pixels, the reverse-biased N-type layer also has a width corresponding to a plurality of pixels. Captured by the mold layer, an almost complete blooming prevention effect can be obtained.

  FIG. 4 is a cross-sectional view of a main part of a solid-state imaging device according to the second embodiment of the present invention. However, the same parts as those in the first embodiment will be described with the same reference numerals. The configuration of the solid-state imaging device of this embodiment is almost the same as that of the first embodiment shown in FIG. 1, but the structure of the pixels arranged in the unquestioned region is different, and FIG. 4 is a diagram showing it. That is, pixels are formed on the N-type silicon substrate 40 by the power supply line portion 44, the floating diffusion portion (FD) 43, and the photodiode portion (PD) 42. When this pixel is formed, N-type is implanted into the P-well region 41 on the N-type silicon substrate 40 in the absence of polysilicon for forming the reset gate and transfer gate, so that the photodiode portion 42 and the floating gate are formed. The entire area between the diffusion portion 43 and the power supply line portion 44 is also an N-type region, and all the regions of the floating diffusion portion 43, the photodiode portion 42, and the power supply line portion 44 are N-type regions. As a result, the floating diffusion portion 43 and the photodiode portion 42 are electrically connected to the power supply line portion 44. Therefore, as shown in the figure, the pixels forming the unquestioned regions do not have reset gates or transfer gates, and all the pixel portions are N-type regions.

  According to the present embodiment, the photodiode portion 42 and the floating diffusion portion 43 that form pixels in the unquestioned region are electrically connected to the power supply line portion 44, and this portion functions as a reverse-biased N-type layer. In other words, since the entire active portion of the pixel plays the same role as the power supply line portion, the charge that flows from the light receiving portion pixel to the OPB pixel as in the first embodiment is not affected. The reverse-biased N-type layer can capture and discharge the captured charge through the power supply line portion 44. Therefore, blooming can be prevented and the same effect as that of the first embodiment can be obtained. . In particular, in this embodiment, a CMOS image sensor is configured because a reverse-biased N-type layer is always generated without applying a voltage to the reset gate and transfer gate as in the first embodiment. It does not damage the oxide film and shorten its life.

  Further, since the present embodiment also uses an originally unquestioned region as a reverse-biased N-type layer, the continuity between the OPB pixel and the light receiving unit pixel is not impaired except for the gate unit. In order to make the pixel in the unquestioned region N-type as described above, it is only necessary to change the mask pattern, and there is no need to change the manufacturing process. It can be changed like the form.

  FIG. 5 is a cross-sectional view of a main part of a solid-state imaging device according to the third embodiment of the present invention. However, the same parts as those in the first embodiment will be described with the same reference numerals. The configuration of the solid-state imaging device of this embodiment is almost the same as that of the first embodiment shown in FIG. 1, but the structure of the photodiode portion of the pixels arranged in the unquestioned region is different, and FIG. 5 shows it. FIG.

  That is, the P ++ region of the photodiode portion 42 that constitutes the pixel in the unquestioned region of this embodiment and the lower part of the N + region in the N + region are directly formed on the N-type silicon substrate 40, and originally exist as shown in FIG. The P-type well region 41 is eliminated. As a result, since the photodiode portion 42 is electrically connected to the N-type silicon substrate 40, the charge that flows from the light-receiving portion pixel to the OPB pixel is captured by the photodiode portion 42 in the unquestioned region. And flows to the N-type silicon substrate 40. The structure as shown in FIG. 5 can be easily formed if the P-type well is not implanted into the portion where the photodiode portion 42 is formed by the mask when forming the P-type well, and there is no need to change the manufacturing process. .

  According to the present embodiment, the photodiode portion 42 that constitutes the pixel in the unquestioned region is configured to be electrically connected to the N-type silicon substrate 40, so that the charge that flows from the light receiving portion pixel to the OPB pixel can be reduced. It can be captured by the photodiode portion 42 in the unquestioned region and discharged to the N-type silicon substrate 40 side, and there is an effect similar to that of the first embodiment.

  In the above embodiment, only the photodiode portion 42 is directly connected to the N-type silicon substrate 40. However, as shown in FIG. 7, the P-type that is between the floating diffusion portion 43 and the N-type silicon substrate 40 is used. By eliminating the well region and forming the floating diffusion portion 43 directly on the N-type silicon substrate 40, the same effect as the structure shown in FIG. 6 can be obtained. In other words, the floating diffusion portion 43 is electrically connected to the N-type silicon substrate 40, so that the charge that flows from the light-receiving portion pixel to the OPB pixel is not affected by the photodiode portion 42 and the floating diffusion portion 43. Since the charges overflowing from the light receiving portion pixels can be captured by the unquestioned region by capturing both of them and flowing them to the N-type silicon substrate 40, blooming can be prevented. In some cases, a certain effect can be obtained even if a structure in which only the floating diffusion portion 43 is electrically connected to the N-type silicon substrate 40 is adopted. In the case of the structure shown in FIGS. 5 and 7, the reset gate and the transfer gate need not be formed.

  In addition, the present invention is not limited to the above-described embodiment, and can be implemented in various other forms in specific configurations, functions, operations, and effects without departing from the gist thereof. For example, the photodiode portion 42 of the first and second embodiments of the present invention shown in FIGS. 2 and 4 has the configuration of the third embodiment shown in FIG. The floating diffusion portion 43 of the embodiment is configured as a modification of the third embodiment shown in FIG. 7, and both the photodiode portion 42 and the floating diffusion portion 43 of the first and second embodiments of the present invention are used. As shown in FIGS. 5 and 7, the prevention of blooming can be brought closer to perfection.

1 is a schematic plan view of a solid-state imaging device according to a first embodiment of the present invention. It is a fragmentary sectional view of the unquestioned region shown in FIG. FIG. 2 is a circuit diagram illustrating a circuit configuration of a light receiving unit illustrated in FIG. 1. It is principal part sectional drawing of the solid-state image sensor which concerns on the 2nd Embodiment of this invention. It is principal part sectional drawing of the solid-state image sensor which concerns on the 3rd Embodiment of this invention. It is principal part sectional drawing which showed the structure of the photodiode part which forms the pixel of the light-receiving part of the solid-state image sensor of 3rd Embodiment. It is principal part sectional drawing which showed the modification of the 3rd Embodiment of this invention. It is a figure explaining the electric charge which flows into the OPB pixel from the light-receiving part pixel in the conventional solid-state image sensor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Photoelectric conversion element, 2 ... Amplifying transistor, 3 ... Transfer transistor, 4 ... Reset transistor, 5 ... Power supply potential supply line, 6 ... Selection transistor, 7 ... Pixel output line, 8 ... Constant current generating transistor, 9... Transfer signal wiring, 10... Reset signal wiring, 11... Selection signal line, 12... Constant potential supply line, 13, 16, 18. , 19 ... AND element for row selection, 15 ... Vertical selection means, 20 ... CDS circuit, 21 ... Column selection means, 31 ... Light receiving part, 32 ... OPB part, 33 ... Unquestioned area, 40 ... ... N-type silicon substrate, 41 ... P-type well region, 42 ... Photodiode part (PD), 43 ... Floating diffusion part (FD), 44 ... Power line part, 45 ... Reset gate, 46 ... Transfer game .

Claims (3)

A semiconductor substrate;
A light receiving portion that is formed on the semiconductor substrate and that arranges pixels that photoelectrically convert incident light to accumulate charges; and
A light-shielding portion formed on the semiconductor substrate and arranged for light-shielded pixels;
Formed between the light-receiving portion and the light-shielding portion on the semiconductor substrate, and an unquestioned region portion in which dummy pixels are arranged,
The photoelectric conversion unit constituting the dummy pixel, the reading unit for reading out the electric charge photoelectrically converted by the photoelectric conversion unit, and the power supply line unit for supplying the operation power of the pixel are always electrically connected ,
On the surface of the semiconductor substrate in the dummy pixel, there are provided a transfer gate for controlling transfer of charges obtained by photoelectric conversion by the photoelectric conversion unit, and a reset gate for resetting the readout unit. A solid-state imaging device in which a predetermined voltage is constantly applied to the transfer gate and the reset gate . The predetermined voltage is the same as a power supply voltage supplied to the solid-state imaging device or a selection voltage for selecting a charge readout pixel.
The solid-state imaging device according to claim 1 . The dummy pixels in the unquestioned region portion have the same configuration as the pixels in the light receiving portion and the light shielding portion
The solid-state imaging device according to claim 1 or 2 .

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