JP2002334983A - Laminated type solid-state imaging device and camera using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated type solid-state imaging device that can obtain high multiplication factors, without using any high-breakdown-voltage transistors, and to provide a camera using the laminated type solid-state imaging device. SOLUTION: At a photoelectric conversion section 105 comprising a translucent substrate 101, a translucent conductive film 102 formed on the translucent substrate 101, and a photoelectric conversion film 103 which is mainly made of an amorphous semiconductor, a protective resistance layer 105 composed mainly of an amorphous semiconductor is formed. The protection resistance layer is joined to a pixel electrode 107 on a scanning circuit section 106, that is formed on another substrate and has a scanning circuit by an indium bump 108 or the like. Also, the photoelectric conversion film 103 has a hole-blocking reinforcement layer 1031 for blocking injection of holes, and an electron-blocking reinforcement layer 1032 for blocking injection of electrons.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a stacked solid-state imaging device having a protective resistance layer between a photoelectric conversion unit and a pixel transistor, and a camera using the stacked solid-state imaging device.

[0002]

2. Description of the Related Art FIG.
(High Avalanche Rushing a
1 shows a stacked solid-state imaging device using a morphous photoconductor.

FIG. 1A shows an example of the overall configuration, including a horizontal scanning circuit 11 for performing horizontal scanning, a correlated double sampling circuit (CDS circuit) 12 for removing noise from a read signal, and
It has a line amplifier 13 for amplifying the read signal, a photoelectric conversion unit 14 for converting an optical signal into an electric signal, and a vertical scanning circuit 16 for performing vertical scanning.

FIG. 1B shows a configuration example of the pixel section 15 of the photoelectric conversion section 14. FIG. 1B shows a HARP film 21,
It comprises a pixel transistor 24 and a storage diode 23. FIG. 2 illustrates a structural example of one pixel in FIG. In addition, 211 is a transparent electrode, and HA
The RP film has a hole blocking enhancement layer 212 for preventing hole injection and an electron blocking enhancement layer 213 for preventing electron injection. The storage diode 23 is a diode formed between the drain D and the substrate when the drain D of the pixel transistor 24 is formed.

The holes generated by the light incident on the HARP film 21 are subjected to avalanche multiplication in the HARP film,
The electrons flow into the storage diode 23 of each pixel (electrons decrease by recombination), and the potential of the storage diode 23 increases according to the signal level. At this time, in the pixel selected by the scanning circuit, the pixel transistor 24 conducts, and a current flows through the signal line so as to compensate for the lost electrons. This current (a signal of a current corresponding to the amount of light incident on the HARP film 21) is amplified by a line amplifier 13 provided for each column, noise is removed by a CDS circuit 12, and then output. A signal having a high SN ratio can be obtained.

Heretofore, it has been essential to use a high-voltage MOS transistor as the pixel transistor 24 of the stacked solid-state imaging device. This is because the photoelectric conversion film used is a blocking type photoelectric conversion film and further amplifies signal charges by utilizing the avalanche effect of charge avalanche. The reason will be described below.

That is, in order to operate this photoelectric conversion film with a high signal multiplication factor, it is necessary to generate a relatively high electric field in the photoelectric conversion film. For example, when a photoelectric conversion film mainly composed of amorphous selenium (a-Se) is used, this electric field requires an electric field intensity of about 10 ⁸ V / m. In order to obtain a multiplication factor of twice, the applied voltage needs to be about 60V. Further, in order to obtain a higher multiplication factor, it is necessary to increase the traveling distance of the electric charge, so that it is necessary to increase the thickness of the photoelectric conversion film, and accordingly, the applied voltage needs to be further increased. For example, an avalanche multiplication factor of 800
In order to double the size, when the photoelectric conversion film is 25 μm,
It is necessary to set the applied voltage to 2500 V.

In a normal operation when an ideal photoelectric conversion film is used, the drain voltage of a pixel transistor electrically connected to a pixel of the photoelectric conversion film may not exceed the withstand voltage of the transistor (for example, about 18 V). Therefore, there is no need to increase the breakdown voltage of the pixel transistor.

However, when a photoelectric conversion film is manufactured, actually, a slight defect occurs in the photoelectric conversion film,
As will be described later, a voltage higher than the withstand voltage of a normal transistor may be applied to the drain of the transistor.

The causes of the defects are considered to be protrusions existing in the light-transmitting substrate or the light-transmitting conductive film, impurities mixed during the deposition of the photoelectric conversion film, and the like. It is difficult.

[0011] Therefore, it is appropriate to design the scanning circuit portion on the assumption that the photoelectric conversion film has some defects. In order to consider this, simplified circuit diagrams of one conventional pixel are shown in FIGS.

The power supply voltage applied to the photoelectric conversion film is V _ITO
And then, Tr pixel transistor in the figure, the drain and the resistance value between the substrates of R _DB pixel transistor, C _DB denotes the capacitance value between the drain of the pixel transistor and the substrate. The photoelectric conversion film can be considered as a current source that depends on the amount of incident light and the applied voltage (V _ITO ).

[0013] If the photoelectric conversion film is operating normally, as in FIG. 3 (A), V _{IT O} via a current source 10, is applied to the drain D of the pixel Bok transistor Tr . In this case, the power supply voltage of the V _ITO is divided by a resistor and R _DB of the current source 10 is applied to the drain D of the pixel Bok transistor Tr. The resistance of the current source 10, as compared to R _DB, because it exhibits a large resistance value, the high voltage to the drain D of the pixel transistor Tr is not applied.

However, when a defect exists, FIG.
As shown in (B), the resistance drops at the defective portion, and the high voltage V _ITO may be directly applied to the drain of the pixel transistor in some cases. It is necessary to use a high breakdown voltage MOS transistor capable of withstanding such a high voltage.

For this reason, as a conventional pixel transistor, as shown in FIG. 4, a DDD (Double Dif) is used.
A high-breakdown-voltage MOS transistor in which an electric field relaxation layer is arranged on the drain side, such as a fused drain, has been applied. FIG. 4 includes a gate electrode 202, a source electrode 201, a drain electrode 203, a source 204, a drain 205, and an electric field relaxation layer 206. Source 2
04 and the drain 205 are n ⁺ and the electric field relaxation layer 2
06 n ^- a.

The breakdown voltage of such a high breakdown voltage MOS transistor depends on the distance L of the electric field relaxation layer 206 and the impurity concentration of the electric field relaxation layer n ⁻ , more precisely, between the drain diffusion layer and the substrate when a voltage is applied to the drain electrode. Depends on the width of the depletion layer formed in the substrate. In the conventional high breakdown voltage MOS transistor, the maximum breakdown voltage of about 60 V is obtained by setting the electric field relaxation layer to 3 μm, which is about three times as large as that of a normal MOS transistor.

This high breakdown voltage MOS transistor was applied to a pixel portion, and a prototype was actually produced. In this stacked solid-state imaging device, a bias voltage of 60 V
The photoelectric conversion film thickness was set to 0.4 μm so that avalanche multiplication factor of 5 was obtained.

[0018]

However, in the prototyped solid-state imaging device, as long as the maximum voltage applied to the photoelectric conversion film is limited by the withstand voltage of the high-voltage MOS transistor, a higher avalanche multiplication factor cannot be obtained. I can't hope. In addition, when the film thickness is as thin as the current photoelectric conversion film of 0.4 μm, the film defect or dark current increases, and the output image has many pixel defects, which is not suitable, and the entire scanning circuit portion is not suitable. Causes destruction. It is considered that the destruction of the scanning circuit portion is caused by increasing the breakdown voltage of only the pixel transistors. That is, if the entire circuit is operated in a state where a high voltage of 60 V is applied to the drain of the pixel transistor, a relatively high voltage is also applied to the amplifier connected from the source of the pixel transistor to the end.
In order to solve this problem, it is necessary to increase the withstand voltage of the transistor or the capacitor of the amplifier section as the withstand voltage of the pixel transistor is increased, but it is difficult in practice.

Further, when considering the increase in the number of pixels of the stacked solid-state imaging device, it is necessary to reduce the pixel pitch. However, the accompanying miniaturization of the pixel transistor causes a decrease in withstand voltage. Since the breakdown voltage necessarily depends on the distance of the depletion layer between the drain region and the substrate, simply miniaturizing a transistor having a structure like DDD inevitably lowers the breakdown voltage of the high breakdown voltage MOS transistor.

As described above, in the stacked solid-state imaging device,
The above-described problem occurs when simply increasing the breakdown voltage of the pixel transistor is performed. To solve this, another solution is needed.

The present invention has been made in view of the above problems, and has as its object to provide a stacked solid-state imaging device capable of obtaining a high multiplication factor without using a high-breakdown-voltage pixel transistor and a camera using the same. And

[0022]

In order to solve the above problems, the present invention employs means for solving the problems having the following features.

According to the first aspect of the present invention, a photoelectric conversion unit having a light-transmitting conductive film formed on a light-transmitting substrate and a photoelectric conversion film mainly composed of a semiconductor is different from the light-transmitting substrate. In a stacked solid-state imaging device having a scanning circuit portion formed over a substrate, a protection resistance layer that protects the photoelectric conversion portion and the scanning circuit portion is provided between the photoelectric conversion portion and the scanning circuit portion. It is characterized by having.

According to a second aspect of the present invention, in the stacked solid-state imaging device according to the first aspect, the current flowing through the protective resistance layer is set when the breakdown of a pixel transistor provided in the scanning circuit section starts. , Or a current value lower than the current value.

According to a third aspect of the present invention, in the stacked solid-state imaging device according to the first or second aspect, the protective resistance layer is mainly made of an amorphous semiconductor.

According to a fourth aspect of the present invention, a photoelectric conversion unit having a light-transmitting conductive film formed on a light-transmitting substrate and a photoelectric conversion film mainly composed of a semiconductor is different from the light-transmitting substrate. In a stacked solid-state imaging device having a scanning circuit portion formed on a substrate and a joining portion that joins the photoelectric conversion portion and the scanning circuit portion, between the joining portion and the photoelectric conversion portion and / or A protection resistor layer for protecting the photoelectric conversion unit and the scanning circuit unit is provided between the junction and the scanning circuit unit.

According to a fifth aspect of the present invention, in the stacked solid-state image pickup device according to the fourth aspect, a charge is provided on the side of the protective resistance layer provided between the junction and the photoelectric conversion part on the side of the junction. An injection layer is provided.

According to a sixth aspect of the present invention, in the stacked solid-state imaging device according to the fourth or fifth aspect, the bonding portion is manufactured by using a bump bonding method.

According to a seventh aspect of the present invention, there is provided a camera using the stacked solid-state imaging device according to any one of the first to sixth aspects.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 is a sectional view showing a state in which the photoelectric conversion unit and the scanning circuit unit, and the photoelectric conversion unit and the scanning circuit unit are pressure-bonded to each other in a basic embodiment of the stacked solid-state imaging device according to the present invention. is there. FIG. 5 shows a light-transmitting substrate 101 such as glass,
A light-transmitting conductive film 102 formed over a light-transmitting substrate 101;
A protective resistance layer 105 mainly composed of an amorphous semiconductor is formed in a photoelectric conversion portion 105 composed of a photoelectric conversion film 103 mainly composed of an amorphous semiconductor, and a scanning circuit formed on a different substrate from this is formed. Pixel electrode 107 on the scanning circuit portion 106 having
And an indium bump 108 or the like.
Note that the photoelectric conversion film 103 includes a hole blocking enhancement layer 1031 for preventing injection of holes and an electron blocking enhancement layer 1032 for preventing injection of electrons.

In FIG. 5, a transparent electrode 102 is formed on a light-transmitting substrate 101, a photoelectric conversion film 103 for generating a signal charge according to incident light from the outside is formed thereon, and a photoelectric conversion section 104 is formed. Make up. On this, a-Se, which is an amorphous semiconductor, is further laminated at 1 μm, and this is used as a protective resistance layer 105.

The present invention mainly aims at protecting the photoelectric conversion unit and the scanning circuit unit by interposing a relatively high protection resistance layer 105 between the photoelectric conversion film and the pixel electrode.
At this time, the resistance value (Rpt) for one pixel needs to satisfy the following condition. In other words:-It does not affect the avalanche operation of the photoelectric conversion film.-The charges generated in the photoelectric conversion film are accumulated in the drain region without delay. Excessive current does not flow in the defective portion of the photoelectric conversion film. Therefore, the required resistance value varies depending on the voltage applied to the photoelectric conversion film, the capacitance between the drain region of the pixel transistor and the substrate (accumulation diode capacitance), the accumulation time, and the current value to be controlled in the pixel defect portion. In consideration of the breakdown characteristics of the pixel transistor, for example, 1 ×
It is set to be about 10 ¹⁴ Ω.

From another viewpoint, the current flowing through the protective resistance layer does not affect the avalanche operation of the photoelectric conversion film. The electric charge generated in the photoelectric conversion film is accumulated in the drain region without delay. The current value may be set so that an excessive current does not flow in the defective portion of the photoelectric conversion film. From this perspective,
The current value at the start of the breakdown of the pixel transistor or a current value lower than that may be used. Here, the current value at the start of the breakdown of the pixel transistor is defined as when a forward potential is applied to the drain electrode.
It means a current value from when the drain current starts flowing until the drain current rises.

As the protective resistance, it is preferable to form a film mainly composed of an amorphous semiconductor by a vacuum evaporation method or sputtering, etc., and to form a resistance layer. In some cases, a resistance layer may be formed on the scanning circuit portion side. For this protective resistance layer, not only a-Se but also an amorphous semiconductor such as a-Si can be used.

On the other hand, reference numeral 106 denotes a semiconductor substrate made of silicon or the like, on which a plurality of MOS transistors are arranged in an array, and the drain side of which is connected to the pixel electrode 107 through a metal wiring. An In bump is formed on each of the pixel electrodes, and the photoelectric conversion unit 105 is formed through the In bump.
And the scanning circuit unit 106 are electrically connected to each other to obtain a stacked solid-state imaging device.

The manufacturing process as a whole is as follows.
A protective resistance layer mainly composed of an amorphous semiconductor is formed on a photoelectric conversion portion composed of a light-transmitting conductive film formed on a light-transmitting substrate and a photoelectric conversion film mainly containing a semiconductor, and the light-transmitting substrate and Connects a scanning circuit formed on another different substrate and a scanning circuit portion having a pixel electrode by bump bonding. The resistance value required for the protective resistance layer is the voltage applied to the photoelectric conversion film, the drain-substrate capacitance (storage diode capacitance) of the pixel transistor,
Depending on the accumulation time and the current value to be limited in the pixel defective portion, the photoelectric conversion film is 1 μm and the protective resistance layer is 1 μm as described in the following examples. Note that the present invention can be implemented without being limited to a photoelectric conversion film of 1 μm and a protective resistance layer of 1 μm.

[0038] if the photoelectric conversion layer is operating normally, as in FIG. 6 _{(A), V IT O} via a current source 10 and the protection resistor _{R PT,} applied to the pixel Bok transistor Tr Is done. In this case, as for the power supply voltage of V _ITO, a high voltage is not applied to the drain D of the pixel transistor, as in FIG. 3A, since the protection resistor _RPT is inserted in series with the resistance of the current source 10. .

Even if a defect exists, as shown in FIG. 6B, a high-voltage V _ITO is applied to the protection resistors _RPT and _{RPT at} the drain D of the pixel transistor.
_{The data} is divided and applied by the _DB . Protection resistance R
_PT, compared to R _DB, because it exhibits a large resistance value, the high voltage to the drain D of the pixel transistor Tr is not applied.

FIG. 7 shows the characteristics of the prototyped solid-state imaging device manufactured under these conditions. As a result, in this imaging apparatus, an avalanche multiplication factor of about 10 was confirmed when 160 V was applied. This exceeds the conventional multiplication factor of 5 times. Furthermore, when a case where a pixel defect was present when the voltage of 160 V was applied was examined, it was confirmed that the destruction of the scanning circuit portion was reduced as compared with the conventional type, and the operation was more stable.

As shown in FIG. 8, the above-described protective resistance layer 10
5 is provided, in order to facilitate charge injection from the scanning circuit side, Li is added to a-Se on the electrode side of the protective resistance layer 105.
It is also preferable to form a layer doped with P to form the charge injection layer 109.

In this case, the protection resistance layer and the metal electrode form a Schottky junction, and the protection resistance layer has a very high resistance. As a result, no voltage is applied to the photoelectric conversion film that should be applied. Do to avoid things.
Of course, the resistance value of the protective resistance layer at this time should be adjusted so as to have the above-described value.

FIG. 9 shows the influence of the charge injection layer. Is the characteristic when the charge injection layer is not added (the HARP film is 1 μm and the protective resistance layer (Se layer) is 1 μm). The avalanche voltage is very high, almost the same as when the HARP film is 2 μm. LiF of charge injection layer (LiF doped layer)
When the concentration is 5000 ppm, the characteristic becomes
The avalanche voltage decreases. By increasing the LiF concentration,
When it is set to 10000 ppm, the following characteristic is obtained, and the avalanche voltage is further reduced. Thus, LiF
As the concentration increases, the avalanche voltage decreases,
It approaches (the characteristic of) the case where the normal HARP film is 1 μm.

FIG. 10A shows a band structure without the charge injection layer, and FIG. 10B shows a band structure with the charge injection layer.

When no charge injection layer is provided (protective resistance layer a
-Se and the joint In are Schottky joints. In (2), a voltage drop of the same level as that of the photoelectric conversion unit occurs in the protective resistance layer. As a result, the avalanche voltage corresponding to the total thickness of the protection resistance layer and the electric conversion unit is obtained, and the voltage becomes high.

On the other hand, when a charge injection layer is provided, LiF
Doping increases the Fermi level of the protective resistance layer and facilitates the injection of electrons. Further, when electrons are sufficiently injected, the voltage drop in the protective resistance layer becomes small, and accordingly, the voltage drop in the photoelectric conversion unit becomes large. As a result, the avalanche doubling region in the entire film has a low voltage.

In the above embodiment, an example was described in which a protective resistance layer was provided between the junction and the photoelectric conversion unit. Alternatively, a protection resistance layer was provided between the junction and the scanning circuit. You may. Further, a protective resistance layer may be provided between the junction and the photoelectric conversion unit and between the junction and the scanning circuit unit.

In the above embodiment, the case where bump bonding is performed has been described. However, the present invention can be applied to a case where bump bonding is not performed.

As described in detail above, according to the embodiment of the present invention, it is possible to further increase the voltage applied to the photoelectric conversion unit, which is conventionally limited by the withstand voltage of the high withstand voltage MOS transistor. A higher multiplication factor can be obtained. That is, since the withstand voltage required for the pixel transistor can be reduced, the avalanche multiplication factor of the photoelectric conversion unit can be increased by increasing the thickness of the photoelectric conversion unit and applying a high voltage.

Further, it is possible to reduce the instability of the circuit and the destruction of the circuit caused by using the high-voltage MOS transistor in the pixel portion.

Further, it is possible to reduce the pixel pitch, which is difficult with a high breakdown voltage MOS transistor, and it is possible to increase the number of overlapping pixels and increase the definition. As a result, a high-sensitivity, high-definition, and stable photoelectric conversion film stack-type imaging device combining the advantages of a small, thin, and excellent operability solid-state imaging device with the advantages of an imaging device using a photoelectric conversion film having a blocking structure. Can be obtained.

[0052]

According to the present invention, it is possible to provide a stacked solid-state imaging device capable of obtaining a high multiplication factor without using a high breakdown voltage pixel transistor and a camera using the same.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a stacked solid-state imaging device.

FIG. 2 is a diagram illustrating a conventional example of a structure for one pixel.

FIG. 3 is a diagram for explaining a conventional circuit diagram for one pixel. (A) shows a normal operation, and (B) shows a breakage of the photoelectric conversion film.

FIG. 4 is a diagram illustrating an example of a conventional high-voltage MOS transistor provided in a pixel portion.

FIG. 5 is a diagram for explaining an embodiment (part 1) of the present invention.

FIG. 6 is a diagram for explaining a circuit diagram of one pixel of the present invention. (A) shows a normal operation, and (B) shows a breakage of the photoelectric conversion film.

FIG. 7 is a diagram for explaining characteristic evaluation of a prototype device of the present invention.

FIG. 8 is a diagram for explaining an embodiment (part 2) of the present invention.

FIG. 9 is a diagram for explaining the influence of a charge injection layer.

FIG. 10 is a diagram for explaining a band when a charge injection layer is provided.

[Explanation of symbols]

Reference Signs List 10 current source 11 horizontal scanning circuit 12 correlated double sampling circuit (CDS circuit) 13 line amplifier 14 photoelectric conversion unit 15 pixel unit 16 vertical scanning circuit 21 HARP film 23 storage diode 24 pixel transistor 101 translucent substrate 102 translucent Conductive conductive film 103 Photoelectric conversion film 104 Photoelectric conversion section 105 Protective resistance layer 106 Scanning circuit section 107 Pixel electrode 108 Bump section 201 Source electrode 202 Gate electrode 203 Drain electrode 204 Source diffusion layer 205 Drain diffusion layer 206 Electric field relaxation layer 211 Transparent electrode 212 , 1031 hole blocking reinforcing layer 213,1032 voltage Tr pixel transistor R _DB pixel transistor the drain and the resistance value R _PT protective resistor C _DB drain between the substrates to be applied to the electron-blocking reinforcing layer V _ITO photoelectric conversion film Emissions and the capacitance value D drain S source G gates between substrates

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Yuichi Ishiguro 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Research Institute (72) Inventor Kozo Moroboshi 1-10-11 Kinuta, Setagaya-ku, Tokyo No. Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Hiroki Matsushita 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Research Institute (72) Inventor Hiroshi Ohtake 1-10 Kinuta, Setagaya-ku, Tokyo No. 11 Japan Broadcasting Corporation Broadcasting Research Laboratory (72) Inventor Hideki Kokubu 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Research Laboratories F-term (reference) 4M118 AA10 AB01 BA07 BA19 CA32 CB05 EA01 HA31 5C024 CX04 CX41 GX07 GX19 GY31

Claims (7)

[Claims] 1. A photoelectric conversion unit having a light-transmitting conductive film formed on a light-transmitting substrate and a photoelectric conversion film mainly composed of a semiconductor, and a scanning circuit formed on a substrate different from the light-transmitting substrate. A solid-state imaging device having a protective resistance layer that protects the photoelectric conversion unit and the scanning circuit unit between the photoelectric conversion unit and the scanning circuit unit. Solid-state imaging device. 2. The method according to claim 1, wherein the current flowing through the protection resistance layer is a current value at the start of breakdown of a pixel transistor provided in the scanning circuit section or a current value lower than the current value. Stacked solid-state imaging device. 3. The stacked solid-state imaging device according to claim 1, wherein the protection resistance layer is mainly made of an amorphous semiconductor. 4. A photoelectric conversion unit having a light-transmitting conductive film formed on a light-transmitting substrate and a photoelectric conversion film mainly composed of a semiconductor, and a scanning circuit formed on a substrate different from the light-transmitting substrate. A solid-state imaging device having a unit, and a junction that joins the photoelectric conversion unit and the scanning circuit unit, wherein: between the junction and the photoelectric conversion unit and / or between the junction and the scanning circuit unit A stacked solid-state imaging device, further comprising a protection resistance layer provided between the photoelectric conversion unit and the scanning circuit unit to protect the photoelectric conversion unit and the scanning circuit unit. 5. The stacked solid-state imaging device according to claim 4, wherein a charge injection layer is provided on the junction side of the protective resistance layer provided between the junction and the photoelectric conversion unit. . 6. The stacked solid-state imaging device according to claim 4, wherein the bonding portion is manufactured using a bump bonding method. 7. A camera using the stacked solid-state imaging device according to claim 1.