JPH02257657A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02257657A JPH02257657A JP1079549A JP7954989A JPH02257657A JP H02257657 A JPH02257657 A JP H02257657A JP 1079549 A JP1079549 A JP 1079549A JP 7954989 A JP7954989 A JP 7954989A JP H02257657 A JPH02257657 A JP H02257657A
- Authority
- JP
- Japan
- Prior art keywords
- film
- cover film
- shape
- semiconductor chip
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000013039 cover film Substances 0.000 claims abstract description 36
- 239000010408 film Substances 0.000 abstract description 17
- 230000035882 stress Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000002250 absorbent Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置に関し、
カバー膜のコーナ部の平面形状を工夫して応力を分散さ
せ、コーナ部のクラック発生を防止して耐湿性の向上を
図ることを目的とし、
平面形状が略矩形状をなす半導体チップの配線層の上層
に、非吸水性のカバー膜を設けた構造の半導体装置にお
いて、前記カバー膜の各々のコーナ部分の平面形状を、
多角形状若しくは略円弧形状に形成したことを特徴とし
て構成している。[Detailed Description of the Invention] [Summary] The present invention aims to improve moisture resistance of semiconductor devices by devising the planar shape of the corner portions of the cover film to disperse stress and prevent cracks from occurring at the corner portions. In a semiconductor device having a structure in which a non-water-absorbing cover film is provided on the upper layer of a wiring layer of a semiconductor chip having a substantially rectangular planar shape, the planar shape of each corner portion of the cover film is as follows:
The structure is characterized by being formed into a polygonal shape or a substantially arcuate shape.
本発明は、半導体装置に関し、特に、半導体チップに耐
湿性確保のためのカバー膜を設けた半導体装置に関する
。The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor chip is provided with a cover film for ensuring moisture resistance.
一般に、半導体チップはプラスチソクバソゲージ等によ
って封止されるが、封止工程中の雰囲気ガスに’12M
な水分が含まれていた場合には、この水分の影響を受け
て特性が変化することがある。Generally, semiconductor chips are sealed using plastic gauges, etc., but during the sealing process, atmospheric gas
If it contains moisture, its properties may change due to the influence of this moisture.
そこで、半導体チップに予め非吸水性のカバー膜を設け
ることが行われている。Therefore, a non-water-absorbing cover film is provided on the semiconductor chip in advance.
従来のこの種の半導体装置としては、半導体チップの配
線層の上層に、直接あるいは他の保護膜を介して、非吸
水性のカバーV(例えばPSG膜)を設けたものが知ら
れている。このような構成によれば、封止工程中の雰囲
気ガスに水分が含まれていたとしても、この水分をカバ
ー膜で4断することができ、半導体チップに対する耐湿
性を確保することができる。As a conventional semiconductor device of this type, one is known in which a non-water-absorbing cover V (for example, a PSG film) is provided on the wiring layer of a semiconductor chip, either directly or through another protective film. According to such a configuration, even if the atmospheric gas during the sealing process contains moisture, this moisture can be cut off by the cover film, and the moisture resistance of the semiconductor chip can be ensured.
C発明が解決しようとする課題〕
しかしながら、このような従来の半導体装置にあっては
、そのカバー膜の平面形状が、第5図に示すように、半
導体チップの平面形状(一般に、矩形状)と一致するも
のであったため、例えば、ダイス付時や封止時における
加熱処理の際に、カバー膜(特にコーナ部分)にクラッ
クが発生することがあるといった問題点があった。C Problems to be Solved by the Invention] However, in such conventional semiconductor devices, the planar shape of the cover film is similar to the planar shape of the semiconductor chip (generally rectangular), as shown in FIG. Therefore, there was a problem that, for example, cracks may occur in the cover film (particularly at the corner portions) during heat treatment during attaching the die or sealing.
すなわち、クラック発生の原因は、カバー膜と、このカ
バー膜に接触する他の材料(パンケージ材料や半導体チ
ップの諸材料)との間の熱膨張係数の差異によって、カ
バー膜に熱応力によるストレスが加えられることを1つ
の要因としており、特に、カバー膜の鋭角部ずなわちコ
ーナ部分ムこ、上記ストレスが集中しやすいことが上記
問題点の主な原因である。ちなみに、カバー膜をP S
G膜とした場合、このPSGO熱膨張係数は9X10
−”であり、これに対して、PSGに接触する封止材料
例えば樹脂の熱膨張係数は2X10−’、また、シリコ
ン(St)の熱膨張係数は4X10−’である。In other words, the cause of cracks is that stress due to thermal stress is applied to the cover film due to the difference in thermal expansion coefficient between the cover film and other materials that come into contact with the cover film (pancage material and various materials of semiconductor chips). In particular, the main cause of the above problem is that the stress tends to be concentrated at the acute angle portions, ie, corner portions, of the cover film. By the way, the cover film is P
When used as a G film, the thermal expansion coefficient of this PSGO is 9X10
In contrast, the thermal expansion coefficient of the sealing material, such as resin, in contact with the PSG is 2X10-', and the thermal expansion coefficient of silicon (St) is 4X10-'.
本発明は、このような問題点に鑑みてなされたもので、
カバー膜のコーナ部の平面形状を工夫して応力を分散さ
せ、コーナ部のクラック発生を防止して耐湿性の向−L
を図ることを目的としている。The present invention was made in view of these problems, and
The planar shape of the corners of the cover film is devised to disperse stress, prevent cracks from occurring at the corners, and improve moisture resistance.
The purpose is to achieve this goal.
本発明に係る半導体装置は」二記目的を達成するために
、平面形状が略矩形状をなす半導体チップの配線層の上
層に、非吸水性のカバー膜を設けた構造の半導体装置に
おいて、前記カバー膜の各々のコーナ部分の平面形状を
、多角形状若しくは略円弧形状に形成したことを特徴と
している。In order to achieve the second object, a semiconductor device according to the present invention has a structure in which a non-water-absorbing cover film is provided on an upper layer of a wiring layer of a semiconductor chip having a substantially rectangular planar shape. A feature is that each corner portion of the cover film has a planar shape of a polygon or a substantially arc shape.
本発明では、カバー膜に加えられる熱応力によるストレ
スが、カバー膜のコーナ部分の平面形状に応じて分散さ
れる。したがって、クラックの発生が回避され、耐湿性
の向上が図られる。In the present invention, stress due to thermal stress applied to the cover film is dispersed according to the planar shape of the corner portion of the cover film. Therefore, generation of cracks is avoided and moisture resistance is improved.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第1.2図は本発明に係る半導体装置の第1実施例を示
す図である。FIG. 1.2 is a diagram showing a first embodiment of a semiconductor device according to the present invention.
第1図において、1は半導体チップであり、半導体チッ
プ1には配線層(図示せず)が形成されている。なお、
配線層の上に、例えばプラズマ窒化膜からなる保護膜や
他の膜あるいは電極があってもよい。2は配線層の上層
に設けられた非吸水性のカバー膜(例えばPSG膜、S
iN膜、5iON膜あるいはSin、膜)であり、カバ
ー膜2は例えば半導体チップ1を製作する工程のJaf
&に、マスクを用いて形成される。ここで、マスクは第
2図中の実線で示す形状を有している。すなわち、第2
図において、破線は半導体チップ1の平面形状の外形線
であり、マスク形状(すなわちカバーH々2の平面形状
)は、半導体チップ1の各コーナ部分を切り落とした形
状(具体的には各コーナ毎に2つの角A、Bを有する多
角形状)に相当している。In FIG. 1, 1 is a semiconductor chip, and a wiring layer (not shown) is formed on the semiconductor chip 1. In addition,
A protective film made of, for example, a plasma nitride film, another film, or an electrode may be provided on the wiring layer. 2 is a non-water absorbing cover film (for example, PSG film, S
iN film, 5iON film, or Sin film), and the cover film 2 is, for example, a JaF film in the process of manufacturing the semiconductor chip 1.
& is formed using a mask. Here, the mask has a shape shown by the solid line in FIG. That is, the second
In the figure, the broken line is the outline of the planar shape of the semiconductor chip 1, and the mask shape (that is, the planar shape of the cover H2) is the shape obtained by cutting off each corner of the semiconductor chip 1 (specifically, each corner This corresponds to a polygonal shape with two angles A and B).
このような構成によれば、熱応力によるストレスが、カ
バー膜2の各コーナ毎に、その2つの角A、Bの2点に
分散される。したがって、カバーlF:!2のコーナ部
分での応力集中を回避でき、クラック発生を防止して、
耐湿性の向上を図ることができる。According to such a configuration, stress due to thermal stress is distributed to two points, ie, two corners A and B, for each corner of the cover film 2. Therefore, cover IF:! 2. Stress concentration at the corner part can be avoided, cracks can be prevented,
Moisture resistance can be improved.
なお、カバー膜2のコーナ部の平面形状は、上記実施例
で示したものに限るものではない。要は、応力を分散さ
せるに適した平面形状であればよく、例えば、第3図に
本発明に係る半導体装置の第2実施例を示すように、カ
バー膜の各コーナ部分の平面形状を、4つの角a〜dを
有する多角形状(4つ以上の多角形状であってもよい)
としてもよいし、あるいは、第4図に本発明に係る半導
体装置の第3実施例を示すように、カバー膜の各コーナ
部分の平面形状を円弧状(ここでいう円弧とは、直線以
外の曲線で描かれる円の円周の一部をいい、その円弧の
曲率は必ずしも一定である必要はない)としてもよい。Note that the planar shape of the corner portion of the cover film 2 is not limited to that shown in the above embodiment. In short, any planar shape is sufficient as long as it is suitable for dispersing stress. For example, as shown in FIG. 3, which shows a second embodiment of the semiconductor device according to the present invention, the planar shape of each corner portion of the cover film may be Polygonal shape having four corners a to d (may be a polygonal shape with four or more corners)
Alternatively, as shown in FIG. 4, which shows a third embodiment of the semiconductor device according to the present invention, each corner of the cover film may have a planar shape of an arc (here, an arc is a shape other than a straight line). It refers to a part of the circumference of a circle drawn by a curved line, and the curvature of the arc does not necessarily have to be constant).
すなわち、第2実施例においては、各コーナ毎の応力分
散点をa % dの4点とすることができるので1)↑
1記第1実施例以上に好ましく、また、第3実施例にお
いては、角が形成されないので応力分散の面で最も好ま
しいものとすることができる。That is, in the second embodiment, the stress distribution points for each corner can be set to four points of a % d, so 1) ↑
This embodiment is more preferable than the first embodiment, and since no corners are formed in the third embodiment, it is most preferable in terms of stress distribution.
本発明によれば、カバー膜のコーナ部の平面形状を工夫
して応力を分散させたので、当該コーナ部に発生するク
ランクを防止でき、耐湿性の向上を図ることができる。According to the present invention, since the planar shape of the corner portion of the cover film is devised to disperse stress, it is possible to prevent cranks from occurring at the corner portion, and it is possible to improve moisture resistance.
第1図はそのカバー膜を設けた半導体チップの斜視図、
第2図はそのカバー膜の平面形状を説明する図、第3図
は本発明に係る半導体装置の第2実施例を示すそのカバ
ー膜の平面形状を説明する図、第4図は本発明に係る半
導体装置の第3実施例を示すそのカバー膜の平面形状を
説明する図、第5図は従来の半導体装置を示すそのカバ
ー膜のコーナ部に発生するクラックの説明図である。FIG. 1 is a perspective view of a semiconductor chip provided with the cover film, FIG. 2 is a diagram illustrating the planar shape of the cover film, and FIG. 3 is a cover showing a second embodiment of the semiconductor device according to the present invention. FIG. 4 is a diagram illustrating the planar shape of the film, FIG. 4 is a diagram illustrating the planar shape of the cover film showing the third embodiment of the semiconductor device according to the present invention, and FIG. FIG. 3 is an explanatory diagram of cracks that occur at the corner portions of FIG.
1・・・・・・半導体チップ、 2・・・・・・カバー膜。1... Semiconductor chip, 2...Cover membrane.
第1.2図は本発明に係る半導体装置の第1実施例を示
す図であり、
第1実施例のカバー膜を設けた半導体チップの斜視図第
1図
第3図
第1実施例のカバー膜の平面形状を説明する図92図
第3実施例のカバー膜の平面形状を説明する図Wi4図1.2 is a diagram showing a first embodiment of the semiconductor device according to the present invention. FIG. 1 is a perspective view of a semiconductor chip provided with a cover film of the first embodiment. FIG. 3 is a perspective view of a semiconductor chip provided with a cover film of the first embodiment. Figure 92 for explaining the planar shape of the film; Figure Wi4 for explaining the planar shape of the cover film of the third embodiment.
Claims (1)
層に、非吸水性のカバー膜を設けた構造の半導体装置に
おいて、 前記カバー膜の各々のコーナ部分の平面形状を、多角
形状若しくは略円弧形状に形成したことを特徴とする半
導体装置。[Scope of Claims] In a semiconductor device having a structure in which a non-water-absorbing cover film is provided on an upper layer of a wiring layer of a semiconductor chip having a substantially rectangular planar shape, the planar shape of each corner portion of the cover film is , a semiconductor device characterized in that it is formed in a polygonal shape or a substantially arc shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7954989A JP2833655B2 (en) | 1989-03-30 | 1989-03-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7954989A JP2833655B2 (en) | 1989-03-30 | 1989-03-30 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02257657A true JPH02257657A (en) | 1990-10-18 |
JP2833655B2 JP2833655B2 (en) | 1998-12-09 |
Family
ID=13693088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7954989A Expired - Fee Related JP2833655B2 (en) | 1989-03-30 | 1989-03-30 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2833655B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06196579A (en) * | 1992-12-24 | 1994-07-15 | Kyocera Corp | Package for semicnductor element |
JP2014060318A (en) * | 2012-09-19 | 2014-04-03 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
CN104347682A (en) * | 2013-08-02 | 2015-02-11 | 颀邦科技股份有限公司 | Semiconductor structure |
JP2015056658A (en) * | 2013-09-10 | 2015-03-23 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2016171183A (en) * | 2015-03-12 | 2016-09-23 | 日本電信電話株式会社 | Semiconductor integrated circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5374371A (en) * | 1976-12-15 | 1978-07-01 | Hitachi Ltd | Semiconductor device |
JPS60183745A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
-
1989
- 1989-03-30 JP JP7954989A patent/JP2833655B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5374371A (en) * | 1976-12-15 | 1978-07-01 | Hitachi Ltd | Semiconductor device |
JPS60183745A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06196579A (en) * | 1992-12-24 | 1994-07-15 | Kyocera Corp | Package for semicnductor element |
JP2014060318A (en) * | 2012-09-19 | 2014-04-03 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
CN104347682A (en) * | 2013-08-02 | 2015-02-11 | 颀邦科技股份有限公司 | Semiconductor structure |
JP2015032826A (en) * | 2013-08-02 | 2015-02-16 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2015056658A (en) * | 2013-09-10 | 2015-03-23 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2016171183A (en) * | 2015-03-12 | 2016-09-23 | 日本電信電話株式会社 | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2833655B2 (en) | 1998-12-09 |
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Legal Events
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